SST25VF512-20-4C-SA Microchip Technology, SST25VF512-20-4C-SA Datasheet - Page 10

• Manufacturer Part Number: SST25VF512-20-4C-SA
• Description: Flash 64K X 8 14 us
• Manufacturer: Microchip Technology

Specifications of SST25VF512-20-4C-SA

• Memory Type: NAND
• Memory Size: 512 Kbit
• Architecture: Sectored
• Interface Type: SPI
• Access Time: 20 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 10 mA
• Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Organization: 64 KB x 8
• Lead Free Status / Rohs Status: No RoHS Version Available

Data Sheet
Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4
KByte sector to FFH. A Sector-Erase instruction applied to
a protected memory area will be ignored. Prior to any Write
operation, the Write-Enable (WREN) instruction must be
executed. CE# must remain active low for the duration of
the any command sequence. The Sector-Erase instruction
is initiated by executing an 8-bit command, 20H, followed
by address bits [A
Block-Erase
The Block-Erase instruction clears all bits in the selected 32
KByte block to FFH. A Block-Erase instruction applied to a
protected memory area will be ignored. Prior to any Write
operation, the Write-Enable (WREN) instruction must be
executed. CE# must remain active low for the duration of
any command sequence. The Block-Erase instruction is
initiated by executing an 8-bit command, 52H, followed by
©2005 Silicon Storage Technology, Inc.
FIGURE 7: S
FIGURE 8: B
ECTOR
LOCK
23
-E
-A
-E
RASE
0
RASE
]. Address bits [A
SCK
SCK
CE#
CE#
SO
SO
SI
SI
S
S
EQUENCE
EQUENCE
MODE 3
MODE 0
MODE 3
MODE 0
MSB
MSB
0 1 2 3 4 5 6 7 8
0 1 2 3 4 5 6 7 8
MS
52
20
-A
HIGH IMPEDANCE
12
HIGH IMPEDANCE
]
10
MSB
MSB
(A
sector address (SA
V
cuted. The user may poll the Busy bit in the software status
register or wait T
timed Sector-Erase cycle. See Figure 7 for the Sector-
Erase sequence.
address bits [A
significant address) are used to determine block address
(BA
be driven high before the instruction is executed. The user
may poll the Busy bit in the software status register or wait
T
Erase cycle. See Figure 8 for the Block-Erase sequence.
ADD.
ADD.
BE
IH.
MS
X
CE# must be driven high before the instruction is exe-
), remaining address bits can be V
for the completion of the internal self-timed Block-
= Most Significant address) are used to determine the
15 16
15 16
ADD.
ADD.
23 24
23 24
23
-A
SE
ADD.
ADD.
X
0
]. Address bits [A
), remaining address bits can be V
for the completion of the internal self-
1192 F28.11
1192 F06.12
512 Kbit SPI Serial Flash
31
31
MS
SST25VF512
IL
S71192-08-000
-A
or V
15
] (A
IH
. CE# must
MS
= Most
IL
11/05
or