A25L010-F AMIC, A25L010-F Datasheet - Page 19
![58T1296](/photos/40/61/406111/ge8dip-40_sml.jpg)
A25L010-F
Manufacturer Part Number
A25L010-F
Description
58T1296
Manufacturer
AMIC
Datasheet
1.A25L010-F.pdf
(44 pages)
Specifications of A25L010-F
Memory Type
Flash
Memory Size
1Mbit
Memory Configuration
1M X 1
Interface Type
Serial, SPI
Clock Frequency
100MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
DIP
No. Of Pins
8
Rohs Compliant
Yes
Fast Read Dual Input-Output (BBh)
The Fast Read Dual Input-Output (BBh) instruction is similar
to the Fast_Read (0Bh) instruction except the data is input
and output on two pins, DO and DIO, instead of just DO. This
allows
A25L020/A25L010/A25L512 at twice the rate of standard SPI
devices.
Similar to the Fast Read instruction, the Fast Read Dual
Output instruction can operate at the highest possible
Figure 11. FAST_READ_DUAL_INPUT-OUTPUT Instruction Sequence and Data-Out Sequence
(December, 2010, Version 1.6)
data
DIO
DIO
DO
DO
S
S
C
C
to
Note: Address bits A23 to A18 are Don’t Care, for A25L020.
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
3 2 1 0
High Impedance
Dummy
be
0 1
Address bits A23 to A17 are Don’t Care, for A25L010.
Address bits A23 to A16 are Don’t Care, for A25L512
Byte
transferred
2 3 4
Instruction
7 5 3 1
6 4 2 0
MSB
DIO switches from input to output
Data Out 1
5 6
from
7
MSB
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
7 5 3 1 7 5 3
MSB
22 20 18
23
8
Data Out 2
21 19
the
9
24-Bit Address
10
18
frequency
accomplished by adding four “dummy” clocks after the 24-bit
address as shown in figure 11. The dummy clocks allow the
device’s internal circuits additional time for setting up the
initial address. The input data during the dummy clocks is
“don’t care”. However, the DIO and DO pins should be
high-impedance prior to the falling edge of the first data out
clock.
7
6 4 2
16 17 18 19
Data Out 3
A25L020/A25L010/A25L512 Series
5 3
1
of
0
0
1
MSB
7 5 3 1 7 5 3 1
Data Out 4
f
C
(See
AMIC Technology Corp.
AC
Data Out 5
Characteristics).
MSB
7
This
is