HSP50210JC-52 Intersil, HSP50210JC-52 Datasheet - Page 30

• Manufacturer Part Number: HSP50210JC-52
• Description: Digital Costas Loop 84-Pin PLCC
• Manufacturer: Intersil

Specifications of HSP50210JC-52

• Package: 84PLCC
• Power Supply Type: Analog
• Typical Supply Current: 225 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

NOTE: These processor signals are meant to be representative. The actual shape of the waveforms will be set by the microprocessor used. Verify
that the processor waveforms meet the parameters in “Waveforms” on page 50 to ensure proper operation. The Processor waveforms are not
required to be synchronous to CLK. They are shown that way to clarify the illustration.
10. Load the Write Address Register with 25
1. Load the Write Address Register with 24
2. Load the Read Address Register with 3
3. Read Internal Status Register to monitor SR-7 to determine when the Lock Detector is stopped and ready to be read.
4. SR-7 goes high, indicating the Lock Detector integration cycle is complete, and ready to be read.
5. Read Internal Status Register and find SR-7 = 1; the Lock Detector is ready to be read.
6. Change Read address to (3; 2; 1; 0) for (Phase Error MSW; PE LSW; False Lock MSW; FL LSW) read.
7. End of Internal Status Valid Data.
8. Assert RD to Read Lock Detector Status
9. Load The Write Address Register with 30
BIT
7
6
5
4
counter in the lock detector. The verify counter is not reset and will resume at the stopped value when the lock detector is restarted.
machine mode).
SR-7
A0-2
C0-7
CLK
WR
Lock Detector Stopped and Ready for Reading
(State Machine Control Mode).
0 = Lock Detector not stopped.
1 = Lock Detector stopped, ready for read.
Lock Detector Stopped and Ready for Reading
(Microprocessor Control Mode).
0 = Lock Detector not stopped.
1 = Lock Detector stopped, ready for read.
Carrier Loop Filter Lag Accumulator Load Complete. This bit
is used to determine when a 32-bit load of Carrier Lag
Accumulator is complete. The accumulator load is initialized
by loading the Write Address Register with 13 (decimal) as
described in Table 28.
0 = Load not complete.
1 = Load complete.
Symbol Tracking Loop Filter Lag Accumulator Load
Complete. This bit is used to determine when a 32-bit load of
Symbol
accumulator load is initialized by loading the Write Address
Register with 19 (decimal) as described in Table 34.
0 = Load not complete.
1 = Load complete.
RD
Track
AT END OF
HALT LD
CYCLE
FIGURE 23. PROCESSOR MONITORING INTERNAL STATUS/READING LOCK DETECTOR
24
Lag
4
1
BIT DESCRIPTION
Accumulator
30
FOR READING
ENABLE
LD REG.
5
3
2
SR7=0
TABLE 14. INTERNAL STATUS REGISTER (SR7-0) BIT MAP
dec
dec
dec
dec
3
is
STATUS READS
to halt the Lock Detector after the current integration cycle. This disables the reload of the integration
to enable the Lock Detector Phase Error Accumulator for reading.
4
to restart the Lock Detector.
to initialize Lock Detector Accumulators and Reset the Integration counters. (Not needed for state
INTERNAL
complete.
4
5
SR7=1
6
7
The
HSP50210
8
3
PE
MSW
LOCK DETECTION STATUS READS
6
BIT
2
8
PE
3
2
1
0
LSW
Lock. Carrier Lock state achieved by Lock Detector.
0 = Not locked.
1 = Locked.
Acquisition/Track. Indicates whether the Lock Detector is in
acquisition or tracking mode.
0 = Tracking Mode.
1 = Acquisition Mode.
Reserved.
Frequency Sweep Direction, defined for upper sideband
signals.
0 = UP.
1 = DOWN.
6
8
1
FL
MSW
BIT DESCRIPTION (Continued)
6
0
8
FL
LSW
9
DETECTOR
RESET
LOCK
30
10
4
DETECTOR
RESTART
LOCK
25
July 2, 2008
FN3652.5