GAL6002B-15LP Lattice, GAL6002B-15LP Datasheet - Page 11

• Manufacturer Part Number: GAL6002B-15LP
• Description: SPLD GAL Family 38 Macro Cells EECMOS Technology 5V 24-Pin PDIP
• Manufacturer: Lattice

Specifications of GAL6002B-15LP

• Package: 24PDIP
• Family Name: GAL
• Number Of Macro Cells: 38
• Maximum Propagation Delay Time: 15 ns
• Typical Operating Supply Voltage: 5 V
• Maximum Number Of User I/os: 10
• Re-programmability Support: Yes

INPUT or
I/O FEEDBACK
Sum Term CLK
REGISTERED
OUTPUT
COMBINATORIAL
OUTPUT
INPUT or
I/O FEEDBACK
ICLK (LATCH)
ICLK or
OCLK
Sum Term CLK
INPUT or
I/O FEEDBACK
COMBINATORIAL
OUTPUT
Switching Waveforms
INPUT or
I/O FEEDBACK
OUTPUT
Input or I/O to Output Enable/Disable
Registered Output (Sum Term CLK)
Combinatorial Output
Latched Input
Clock Width
t
t
t
wh1,2
pd3
su1
VALID INPUT
t
wh3
t
t
su4
dis
VALID INPUT
1/
f
t
h1
max2
t
wl1,2
t
t
pd1,2
co4
VALID INPUT
t
h4
t
en
t
wl3
t
co1
11
INPUT or
I/O FEEDBACK
ICLK (REGISTER)
COMBINATORIAL
OUTPUT
OCLK
Sum Term CLK
INPUT or
I/O FEEDBACK
OCLK
REGISTERED
OUTPUT
INPUT or
I/O FEEDBACK
DRIVING AR
REGISTERED
OUTPUT
Sum Term CLK
OCLK
Specifications GAL6002
Registered Output (OCLK)
Asynchronous Reset
Registered Input
t
t
su3
VALID INPUT
t
arw
VALID INPUT
su2
1/
t
ar
f
max1
t
t
co2
h2
t
t
co3
su6
t
t
h3
arr2
t
t
su5
arr1