HD4074329S Renesas Electronics America, HD4074329S Datasheet - Page 50

• Manufacturer Part Number: HD4074329S
• Description: MCU 4-Bit HMCS400 CISC 20KB EPROM 3.3V/5V 64-Pin SDIP
• Manufacturer: Renesas Electronics America

Specifications of HD4074329S

• Package: 64SDIP
• Family Name: HMCS400
• Maximum Speed: 4.5 MHz
• Ram Size: 268 Byte
• Program Memory Size: 20 KB
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 4 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 35
• On-chip Adc: 4-chx8-bit
• Operating Temperature: -20 to 75 °C
• Number Of Timers: 3

HD404328 Series
Timer B (TCBL and TLRL: $00A, TCBU and TLRU: $00B): Eight-bit write-only timer load register
(TLRL and TLRU) and read-only timer counter (TCBL and TCBU) located at the same addresses. The
eight-bit configuration consists of lower and upper digits located at sequential addresses. A block diagram
of timer B is shown in figure 27.
Timer counter B is initialized by writing to timer load register B (TLR). In this case, the lower nibble must
be written to first. The contents of TLR are loaded into the timer counter at the same time the upper nibble
is written to, initializing the timer counter. TLR is initialized to $00 by MCU reset.
The count of timer B is obtained by reading timer counter B. In this case, the upper digit must be read first;
the count is latched when the upper nibble is read. An auto-reload function, input clock source, and
prescaler division ratio of timer B depend on the state of timer mode register B (TMB). When an external
event input is used as the input clock source of TMB, the D
the ZCD or EVENT pin by setting port mode register B (PMRB: $011).
Timer B is initialized to the value set in TMB by software, and is then incremented by one by each clock
input. If an input is applied to timer B after it has reached $FF, an overflow is generated. In this case, if
the auto-reload function is enabled, timer B is initialized to its initial value; if auto-reload is disabled, the
timer is initialized to $00. The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0).
46
EVENT
System
clock
Figure 27 Timer B Free-Running and Reload Operation Block Diagram
ø
PER
Prescaler S (PSS)
Selector
Free-running/
control signal
reload timer
Clock
register B upper
Timer load
8
/ZCD/EVENT pin must be set to function as
(TLRU)
3
Timer/counter B
(TCB)
register B lower
Timer latch
Timer load
register B
(TLRL)
(TLB)
Timer mode
Interrupt request
flag of timer B
register B
(TMB)
Overflow
(IFTB)