CS4331-KS Cirrus Logic Inc, CS4331-KS Datasheet - Page 25

• Manufacturer Part Number: CS4331-KS
• Description: DAC 2-CH Delta-Sigma 18-Bit 8-Pin SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4331-KS

• Package: 8SOIC
• Resolution: 18 Bit
• Conversion Rate: 50 KSPS
• Architecture: Delta-Sigma
• Digital Interface Type: Serial
• Number Of Outputs Per Chip: 2
• Output Type: Voltage
• Full Scale Error: ±10 %FSR

Analog output filter
The recommended single pole filter required for
the CS4330/31/33 has been combined with a
unity gain output buffer (see Figure 2). The ana-
log output filter uses a Motorola MC33202
single supply, dual op-amp. The low pass filter
corner frequency is located at 2 Fs, or 88.2 kHz
and is calculated by:
F
F
Power Supply Circuitry
Power is supplied to the evaluation board by
three binding posts (GND, +5V, +3V/+5V), See
Figure 7. The +5V input supplies power to the
+5 Volt digital circuitry (VD+5), while the
+3V/+5V input supplies power to the Voltage
Level Converter (VD+3/+5), and CS4330/31/33
(VA+3/+5) for evaluation in either +3 or +5 Volt
mode. The op-amp is supplied from the analog
supply (VA+) which can be derived from either
the +5V post (VA+5) or the +3/+5V post
(VA+3/+5) depending upon which Ferrite bead
(L4 or L5) is installed. The evaluation board is
configured with VA+ derived from VA+5 (L5 in-
stalled). To derive VA+ from the +3V/+5V post
(VA+3/+5), remove the Ferrite bead at L5, and
install it at L4.
Input/Output for Clocks and Data
The evaluation board has been designed to allow
the interface to external systems via the 10-pin
header, J1. This header allows the evaluation
board to accept externally generated clocks and
data. The schematic for the clock/data I/O is
shown in Figure 5. The 74HC243 transceiver
functions as an I/O buffer where the CLK
SOURCE jumper determines if the transceiver
operates as a transmitter or receiver.
DS136DB2
2
2
R
15 k
8
||
1
R
|| 6.65 k
9
1
C
29
390 pF
= 88.5 kHz
The transceiver operates as a transmitter with the
CLK SOURCE jumper in the 8412 position.
LRCK, SDATA, and SCLK from the CS8412
will be available on J1. J22 must be in the 0 po-
sition and J23 must be in the 1 position for
MCLK to be an output and to avoid bus conten-
tion on MCLK.
The transceiver operates as a receiver with the
CLK SOURCE jumper in the EXTERNAL posi-
tion. LRCK, SDATA and SCLK on J1 become
inputs. The CS8412 must be removed from the
evaluation board for operation in this mode.
There are 2 options for the source of MCLK in
the External Clock Source mode. MCLK can be
an input with J23 in the 1 position and J22 in the
0 position. However, the recommended mode of
operation is to generate MCLK on the evaluation
board. MCLK becomes an output with LRCK,
SCLK and SDATA inputs. This technique insures
that the CS4330/31/33 receives a jitter free clock
to maximize performance. This can be accom-
plished by installing a crystal oscillator into U5,
see Figure 4 (the socket for U5 is located within
the footprint for the CS8412) and placing J22 in
the 1 position and J23 in the 0 position.
Grounding and Power Supply Decoupling
The CS4330/31/33 requires careful attention to
power supply and grounding arrangements to op-
timize performance. Figure 2 shows the
recommended power arrangements.
CS4330/31/33 is positioned over the analog
ground plane near the digital/analog ground
plane split. These ground planes are connected
elsewhere on the board. This layout technique is
used to minimizing digital noise and to insure
proper power supply matching/sequencing. The
decoupling capacitors are located as close to the
CS4330/31/33 as possible. Extensive use of
ground plane fill on both the analog and digital
sections of the evaluation board yield large re-
ductions in radiated noise effects.
CDB4330, CDB4331, CDB4333
The
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