CS4331-KS Cirrus Logic Inc, CS4331-KS Datasheet - Page 3

• Manufacturer Part Number: CS4331-KS
• Description: DAC 2-CH Delta-Sigma 18-Bit 8-Pin SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4331-KS

• Package: 8SOIC
• Resolution: 18 Bit
• Conversion Rate: 50 KSPS
• Architecture: Delta-Sigma
• Digital Interface Type: Serial
• Number Of Outputs Per Chip: 2
• Output Type: Voltage
• Full Scale Error: ±10 %FSR

SWITCHING CHARACTERISTICS
1 = VA+, CL = 20 pF) Switching characteristics are guaranteed by characterization.
Notes: 5. In Internal SCLK Mode, the Duty Cycle must be 50% 1/2 MCLK Period.
DS136F1
Input Sample Rate
LRCK Duty Cycle (External SCLK only)
MCLK Pulse Width High
MCLK Pulse Width Low
MCLK Pulse Width High
MCLK Pulse Width Low
MCLK Pulse Width High
MCLK Pulse Width Low
External SCLK Mode
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
Internal SCLK Mode
SCLK Period
SCLK rising to LRCK edge
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
SCLK rising to SDATA hold time
6. The SCLK / LRCK ratio may be either 32, 48, or 64.
Parameter
MCLK / LRCK = 256 or 512
MCLK / LRCK = 512
MCLK / LRCK = 512
MCLK / LRCK = 384
MCLK / LRCK = 384
MCLK / LRCK = 256
MCLK / LRCK = 256
MCLK / LRCK = 384
(TA = 25 C; VA+ = 2.7V - 5.5V; Inputs: Logic 0 = 0V, Logic
(Note 5)
(Note 6) t sclkw
Symbol
t sclkw
t sclkh
t sdlrs
t sclkr
t sdlrs
t sclkl
t slrd
t sdh
t sdh
t sdh
t slrs
Fs
512
512
384
128 Fs
1
SCLK
1
1
Min
30
10
15
21
21
35
39
20
20
20
20
20
20
Fs
Fs
Fs
2
1
1
-
15
15
15
CS4330, CS4331, CS4333
t
Typ
sclkw
50
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1000
1000
1000
1000
1000
1000
Max
50
70
-
-
-
-
-
-
-
-
-
-
-
-
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
s
3