CS493253-CL Cirrus Logic Inc, CS493253-CL Datasheet - Page 37

• Manufacturer Part Number: CS493253-CL
• Description: Multi Standard Audio Decoder 44-Pin PLCC
• Manufacturer: Cirrus Logic Inc

Specifications of CS493253-CL

• Package: 44PLCC
• Operating Temperature: 0 to 70 °C

3) After each byte (including the address and each
4) The host should then clock data into the device
DS339PP4
data byte) the host must release the data line
and provide a ninth clock for the CS493XX to
acknowledge. The CS493XX will drive the
data line low during the ninth clock to
acknowledge. If for some reason the CS493XX
does not acknowledge, it means that the last
byte sent was not received and should be resent.
If the resent byte fails to produce an
acknowledge, a stop condition should be sent
and the device should be reset.
most significant bit first, one byte at a time. The
Figure 22. I
WRITE ADDRESS BYTE
WHILE SCCLK IS HIGH
WHILE SCCLK IS HIGH
SET TO 0 FOR WRITE
RAISE SCDIO HIGH
DROP SCDIO LOW
SEND I
SEND DATABYTE
WITH MODE BIT
MORE DATA?
I
2
GET ACK
GET ACK
C STOP:
2
C
2
C START:
®
N
Write Flow Diagram
Y
5) At the end of a data transfer a stop condition
6.1.2.2.Reading in I
A read operation is necessary when the CS493XX
signals that it has data to be read. It does this by
dropping its interrupt request line (INTREQ) low.
When reading from the device in I
protocol will be used whether reading a single byte
or multiple bytes. The examples shown in this
document can be expanded to fit any read situation.
Figure 23
1) An I
2) The host responds by sending an I
3) The start condition is followed by a 7-bit
4) After the falling edge of the serial control clock
CS493XX will (and must) acknowledge each
byte that it receives which means that after each
byte the host must provide an acknowledge
clock pulse on SCCLK and release the data
line, SCDIO.
must be sent. The stop condition is defined as
the rising edge of SCDIO while SCCLK is
high.
CS493XX dropping INTREQ, signaling that it
has data to be read.
condition which is SCDIO dropping while
SCCLK is held high.
address and the read/write bit set high for a
read. The address for the CS493XX defaults to
0000000b. It is necessary to clock this address
in prior to any transfer in order for the
CS493XX to acknowledge the read. In other
words a byte of 0x01 should be clocked into the
device preceding any read. The 0x01 byte
represents the 7 bit address 0000000b and a
read/write bit set to 1 to designate a read.
(SCCLK) for the read/write bit of the address
byte, an acknowledge must be read in by the
host. The CS493XX will drive SCDIO low to
acknowledge the address byte and to indicate
that it is ready for a read operation. If an
2
C
shows a typical I
®
read transaction is initiated by the
CS49300 Family DSP
2
C
®
2
C
®
read sequence
2
C
®
, the same
2
C
®
start
37