CY7C09289-9AI Cypress Semiconductor Corp, CY7C09289-9AI Datasheet - Page 15

• Manufacturer Part Number: CY7C09289-9AI
• Description: SRAM Chip Sync Dual 5V 1M-Bit 64K x 16 20ns/9ns 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09289-9AI

• Package: 100TQFP
• Timing Type: Synchronous
• Density: 1 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 5 V
• Number Of I/o Lines: 16 Bit
• Number Of Ports: 2
• Number Of Words: 64K

Read/Write and Enable Operation
Address Counter Control Operation
Notes:
Document #: 38-06040 Rev. *A
33. “X” = “Don’t Care,” “H” = V
34. ADS, CNTEN, CNTRST = “Don’t Care.”
35. OE is an asynchronous input signal.
36. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle.
37. CE
38. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.
39. Counter operation is independent of CE
Address
OE
A
H
X
X
X
X
X
X
L
n
0
and OE = V
Previous
Address
A
A
CLK
X
X
IL
n
n
; CE
X
1
and R/W = V
IH
CLK
, “L” = V
Inputs
CE
H
X
L
L
L
IL
ADS
IH
.
0
H
H
.
X
L
0
and CE
CNTEN
1
.
H
X
X
L
[33, 34, 35]
CE
H
H
H
X
L
[33, 37, 38, 39]
1
CNTRST
H
H
H
L
R/W
H
X
X
L
X
D
D
D
D
out(n+1)
I/O
out(0)
out(n)
out(n)
I/O
Outputs
High-Z
High-Z
High-Z
Increment
D
0
D
OUT
Mode
Reset
–I/O
Load
Hold
IN
17
Counter Reset to Address 0
Address Load into Counter
External Address Blocked—Counter
Disabled
Counter Enabled—Internal Address
Generation
Deselected
Deselected
Write
Read
Outputs Disabled
[34]
CY7C09279/89
CY7C09379/89
Operation
[36]
[36]
Operation
Page 15 of 18
[+] Feedback