XC3190A-4PQ160C Xilinx Inc, XC3190A-4PQ160C Datasheet - Page 30
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XC3190A-4PQ160C
Manufacturer Part Number
XC3190A-4PQ160C
Description
FPGA XC3100A Family 6K Gates 320 Cells 227MHz CMOS Technology 5V 160-Pin PQFP
Manufacturer
Xilinx Inc
Datasheet
1.XC3190A-4PQ160C.pdf
(76 pages)
Specifications of XC3190A-4PQ160C
Package
160PQFP
Family Name
XC3100A
Device Logic Units
320
Device System Gates
6000
Number Of Registers
928
Maximum Internal Frequency
227 MHz
Typical Operating Supply Voltage
5 V
Maximum Number Of User I/os
138
Ram Bits
64160
Re-programmability Support
Yes
Case
QFP160
Dc
98+
Available stocks
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XC3000 Series Field Programmable Gate Arrays
Notes: 1. The max limit of CCLK Low time is caused by dynamic circuitry inside the FPGA.
Figure 30: Slave Serial Mode Programming Switching Characteristics
7-32
(Output)
DOUT
CCLK
CCLK
DIN
2. Configuration must be delayed until the INIT of all FPGAs is High.
3. At power-up, V
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long V
non-monotonically rising V
after V
CC
Description
To DOUT
DIN setup
DIN hold
High time
Low time (Note 1)
Frequency
has reached 4.0 V (2.5 V for the XC3000L).
CC
must rise from 2.0 V to V
1 T
DCC
CC
Bit n
may require a >6- s High level on RESET, followed by a >6- s Low level on RESET and D/P
2 T
CCD
CC
min in less than 25 ms. If this is not possible, configuration can be delayed by
Bit n - 1
4 T
CCH
3
1
2
4
5
T
T
T
T
T
Bit n + 1
Symbol
F
CCO
DCC
CCD
CCH
CCL
CC
3 T
CCO
5 T
CC
CCL
0.05
0.05
Min
November 9, 1998 (Version 3.1)
60
rise time of >100 ms, or a
0
Max
100
5.0
10
Bit n
Units
MHz
X5379
ns
ns
ns
s
s
R