AD6650ABCZ Analog Devices Inc, AD6650ABCZ Datasheet - Page 34

• Manufacturer Part Number: AD6650ABCZ
• Description: DIVERSITY IF-TO-BASEBAND GSM/EDGE NARROW-BAND RECEIVER
• Manufacturer: Analog Devices Inc

AD6650
Reg.
(Hex)
B
C
Mnemonic
DC Correction Control
AGC Control 0
19 to 13: Upper
Threshold
12 to 8: Lower Threshold
7 to 3: Minimum Period
2: Bypass
1: Interpolate
0: Freeze
3: Force VGA Gain
2: FD_Enable
1: FA_Enable
0: Reserved
Bit
Width
20
7
5
5
1
1
1
4
1
1
1
1
Fine DCC control registers.
Fine DCC integration period.
Fine DCC bypass.
AGC Control Settings.
Fast decay loop enable.
Description
Fine DCC upper threshold. No new dc
estimation is made if the signal is above the
upper threshold.
Fine DCC lower threshold. The maximum
range for the lower limit is 0 dBFS to
138.46 dBFS.
Fine DCC interpolator reduces discontinuity
between the current dc estimate and the
new estimate.
Fine DCC freeze is used to hold the current
dc estimate.
Force the VGA gain to a specific value. This
control line overrides the slow loop, fast
decay loop, and fast attack loop when
enabled.
Fast attack loop enable.
Reserved.
Rev. A | Page 34 of 44
Additional Information
Power-up value is
20’b00000000000000000000
Code
0
1
2
.
.
126
127
0
1
2
.
.
22
23
Code
1
2
3
.
.
30
31
Code
0
1
0
1
0
1
Code
0
1
0
1
Code
0
1
N/A
Level (dBFS)
0 dBFS
−0.75 dBFS
−1.5 dBFS
.
.
−94.5 dBFS
−95.25 dBFS
0 dBFS
−6.02 dBFS
−12.04 dBFS
.
.
−132.44 dBFS
−138.46 dBFS
Integration
Time
2
2
2
.
.
2
2
T
period
Result
Update DCC
estimate
Keep old
estimate
Disabled
Enabled
Disabled
Enabled
Result
Disabled
Enable forced
gain mode
Disabled
Enable fast
decay loop
Result
Disabled
Enable fast
attack loop
1
2
3
30
31
S
× T
× T
× T
= sample
× T
× T
S
S
S
S
S