A1460A-1PQ208C Actel, A1460A-1PQ208C Datasheet - Page 23

• Manufacturer Part Number: A1460A-1PQ208C
• Description: FPGA ACT 3 Family 6K Gates 848 Cells 125MHz 0.8um (CMOS) Technology 5V 208-Pin PQFP
• Manufacturer: Actel

Specifications of A1460A-1PQ208C

• Package: 208PQFP
• Family Name: ACT 3
• Device Logic Gates: 6000
• Device Logic Units: 848
• Device System Gates: 15000
• Number Of Registers: 768
• Maximum Internal Frequency: 125 MHz
• Typical Operating Supply Voltage: 5 V
• Maximum Number Of User I/os: 167
• Maximum Propagation Delay Time: 2.6 ns

Pre dictabl e P er fo rm a nce:
Tig htes t Delay Di st r i b ut i ons
Propagation delay between logic modules depends on the
resistive and capacitive loading of the routing tracks, the
interconnect elements, and the module inputs being driven.
Propagation delay increases as the length of routing tracks,
the number of interconnect elements, or the number of
inputs increases.
From a design perspective, the propagation delay can be
statistically correlated or modeled by the fanout (number of
loads) driven by a module. Higher fanout usually requires
some paths to have longer lengths of routing track.
The ACT 3 family delivers the tightest fanout delay
distribution of any FPGA. This tight distribution is achieved
in two ways: by decreasing the delay of the interconnect
elements and by decreasing the number of interconnect
elements per path.
Actel’s patented PLICE antifuse offers a very low
resistive/capacitive interconnect. The ACT 3 family’s
antifuses, fabricated in 0.8 micron m lithography, offer
nominal levels of 200
capacitance per antifuse.
The ACT 3 fanout distribution is also tighter than alternative
devices due to the low number of antifuses required per
interconnect path. The ACT 3 family’s proprietary
architecture limits the number of antifuses per path to only
four, with 90% of interconnects using only two antifuses.
The ACT 3 family’s tight fanout delay distribution offers an
FPGA design environment in which fanout can be traded for
the increased performance of reduced logic level designs.
This also simplifies performance estimates when designing
with ACT 3 devices.
Table 2 • Logic Module and Routing Delay by Fanout (ns)
(Worst-Case Commercial Conditions)
Speed
ACT 3 –3
FO=1
2.9
FO=2
resistance and 6 femtofarad (fF)
3.2
FO=3
3.4
FO=4
3.7
FO=8
4.8
T iming Charact eris t ics
Timing characteristics for ACT 3 devices fall into three
categories: family dependent, device dependent, and design
dependent. The input and output buffer characteristics are
common to all ACT 3 family members. Internal routing delays
are device dependent. Design dependency means actual
delays are not determined until after placement and routing
of the user’s design is complete. Delay values may then be
determined by using the ALS Timer utility or performing
simulation with post-layout delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets, which
are used for initial design performance evaluation. Critical
net delays can then be applied to the most time-critical
paths. Critical nets are determined by net property
assignment prior to placement and routing. Up to 6% of the
nets in a design may be designated as critical, while 90% of
the nets in a design are typical.
Long Tracks
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows, columns,
or modules. Long tracks employ three and sometimes four
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically up to 6% of nets in a fully
utilized device require long tracks. Long tracks contribute
approximatley 4 ns to 14 ns delay. This additional delay is
represented statistically in higher fanout (FO=8) routing
delays in the data sheet specifications section.
Timing Derating
ACT 3 devices are manufactured in a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process variations. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature, and best-case processing.
Maximum timing parameters reflect minimum operating
voltage, maximum operating temperature, and worst-case
processing.
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