A1460A-1PQ208C Actel, A1460A-1PQ208C Datasheet - Page 25
A1460A-1PQ208C
Manufacturer Part Number
A1460A-1PQ208C
Description
FPGA ACT 3 Family 6K Gates 848 Cells 125MHz 0.8um (CMOS) Technology 5V 208-Pin PQFP
Manufacturer
Actel
Datasheet
1.A1460A-1PQ208C.pdf
(68 pages)
Specifications of A1460A-1PQ208C
Package
208PQFP
Family Name
ACT 3
Device Logic Gates
6000
Device Logic Units
848
Device System Gates
15000
Number Of Registers
768
Maximum Internal Frequency
125 MHz
Typical Operating Supply Voltage
5 V
Maximum Number Of User I/os
167
Maximum Propagation Delay Time
2.6 ns
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A1460A-1PQ208C
Manufacturer:
NSC
Quantity:
306
Company:
Part Number:
A1460A-1PQ208C
Manufacturer:
Microsemi SoC
Quantity:
10 000
A 1415 A, A 14V15 A T i m i ng Ch ar a c t e r is tic s
(Worst-Case Commercial Conditions, V
Notes:
1.
2.
3.
Logic Module Propagation Delays
Parameter
t
t
t
Predicted Routing Delays
t
t
t
t
t
Logic Module Sequential Timing
t
t
t
t
t
t
t
f
PD
CO
CLR
RD1
RD2
RD3
RD4
RD8
SUD
HD
SUD
HD
WASYN
WCLKA
A
MAX
V
For dual-module macros, use t
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
CC
= 3.0 V for 3.3V specifications.
Description
Internal Array Module
Sequential Clock to Q
Asynchronous Clear to Q
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Flip-Flop Data Input Setup
Flip-Flop Data Input Hold
Latch Data Input Setup
Latch Data Input Hold
Asynchronous Pulse Width
Flip-Flop Clock Pulse Width
Flip-Flop Clock Input Period
Flip-Flop Clock Frequency
3
PD
+ t
RD1
2
+ t
PDn
, t
Min.
CO
‘–3’ Speed
0.5
0.0
0.5
0.0
1.9
1.9
4.0
+ t
CC
RD1
Max.
250
= 4.75 V, T
2.0
2.0
2.0
0.9
1.2
1.4
1.7
2.8
+ t
PDn
or t
Min.
‘–2’ Speed
0.6
0.0
0.6
0.0
2.4
2.4
5.0
PD1
+ t
Max.
200
2.3
2.3
2.3
1.0
1.4
1.6
1.9
3.2
J
RD1
A cceler ator Se rie s FP GAs – A CT
= 70 C)
+ t
SUD
Min.
‘–1’ Speed
0.7
0.0
0.7
0.0
3.2
3.2
6.8
, whichever is appropriate.
1
Max.
150
2.6
2.6
2.6
1.1
1.6
1.8
2.2
3.6
‘Std’ Speed 3.3V Speed
Min.
0.8
0.0
0.8
0.0
3.8
3.8
8.0
Max.
125
3.0
3.0
3.0
1.3
1.8
2.1
2.5
4.2
Min.
10.0
0.8
0.0
0.8
0.0
4.8
4.8
Max. Units
™
100
3.9
3.9
3.9
1.7
2.4
2.8
3.3
5.5
3 Fami ly
1
MHz
1-199
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns