WJCE6355 Intel, WJCE6355 Datasheet - Page 15

• Manufacturer Part Number: WJCE6355
• Description: Demodulator 64-Pin LQFP
• Manufacturer: Intel

Specifications of WJCE6355

• Package: 64LQFP
• Operating Temperature: -40 to 85 °C

3
3.1
3.1.1
The primary 2-wire bus serial interface uses pins:
•
•
The 2-wire bus address is determined by a combination of internal settings and applying Vdd or Gnd to the SADD[4:0]
pins:
When the CE6355 is powered up, the RESET pin 9 should be held low for at least 50 ms after Vdd has reached normal
operation levels. As the RESET pin goes high, the logic levels on SADD[4:0] are latched as the 2-wire bus address. ADDR[0]
is the R/W bit.
The circuit works as a slave transmitter with the lsb set high or as a slave receiver with the lsb set low. In receive mode,
the first data byte is written to the RADD virtual register, which forms the register sub-address. The RADD register takes
an 8-bit value that determines which of 256 possible register addresses is written to by the following byte. Not all
addresses are valid and many are reserved registers that must not be changed from their default values. Multiple byte
reads or writes will auto-increment the value in RADD, but care should be taken not to access the reserved registers
accidentally.
Following a valid chip address, the 2-wire bus STOP command resets the RADD register to 00. If the chip address is not
recognized, the CE6355 will ignore all activity until a valid chip address is received. The 2-wire bus START command does
NOT reset the RADD register to 00. This allows a combined 2-wire bus message, to point to a particular read register with
a write command, followed immediately with a read data command. If required, this could next be followed with a write
command to continue from the latest address. RADD would not be sent in this case. Finally, a STOP command should be
sent to free the bus.
When the 2-wire bus is addressed (after a recognized STOP command) with the read bit set, the first byte read out is the
contents of register 00.
3.1.2
The CE6355 has a General Purpose Port that can be configured to provide a secondary 2-wire bus.
Master control mode is selected by setting register SCAN_CTL (0x62) [b3] = 1.
The allocation of the pins is: GPP0 pin 35 = CLK2
*. Please note that in this configuration, this pin is an output only and therefore does not allow a clock-hold function in the slave device.
DATA1 (pin5) serial data, the most significant bit is sent first.
CLK1 (pin 4) serial clock.
Internal/external settings
Normal TNIM settings
Interfaces
2-Wire Bus
Host
Tuner
Address bits
ADDR[7]
Gnd
Gnd
Table 3 - 2-wire bus address
*
, GPP1 pin 36 = DATA2.
Intel Corporation
ADDR[6]
Gnd
Gnd
CE6355
ADDR[5]
SADD[4]
Gnd
ADDR[4]
SADD[3]
Vdd
ADDR[3]
SADD[2]
Vdd
ADDR[2]
SADD[1]
Vdd
Data Sheet
ADDR[1]
SADD[0]
Vdd
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