ADC08831IMX National Semiconductor, ADC08831IMX Datasheet - Page 14

• Manufacturer Part Number: ADC08831IMX
• Description: ADC Single SAR 181KSPS 8-Bit Serial 8-Pin SOIC N T/R
• Manufacturer: National Semiconductor

Specifications of ADC08831IMX

• Package: 8SOIC N
• Resolution: 8 Bit
• Sampling Rate: 181 KSPS
• Architecture: SAR
• Number Of Analog Inputs: 1
• Digital Interface Type: Serial (3-Wire, Microwire)
• Input Type: Voltage
• Signal To Noise Ratio: 48.5(Typ) dB
• Polarity Of Input Voltage: Unipolar

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Functional Description
5.0 THE ANALOG INPUTS
The most important feature of these converters is that they
can be located right at the analog signal source and through
just a few wires can communicate with a controlling proces-
sor with a highly noise immune serial bit stream. This in itself
greatly minimizes circuitry to maintain analog signal accu-
racy which otherwise is most susceptible to noise pickup.
However, a few words are in order with regard to the analog
inputs should the input be noisy to begin with or possibly
riding on a large common-mode voltage.
The differential input of these converters actually reduces
the effects of common-mode input noise, a signal common
to both selected “+” and “−” inputs for a conversion (60 Hz is
most typical). The time interval between sampling the “+” in-
put and then the “−” input is
in the common-mode voltage during this short time interval
can
common-mode signal this error is:
where f
For a 60Hz common-mode signal to generate a
()5mV) with the converter running at 250kHz, its peak value
would have to be 6.63V which would be larger than allowed
as it exceeds the maximum analog input limits.
Source resistance limitation is important with regard to the
DC leakage currents of the input multiplexer. Bypass capaci-
tors should not be used if the source resistance is greater
than 1k . The worst-case leakage current of
perature will create a 1mV input error with a 1k
sistance. An op amp RC active low pass filter can provide
both impedance buffering and noise filtering should a high
impedance signal source be required.
5.1 Sample and Hold
The ADC08831/2 provide a built-in sample-and-hold to ac-
quire the input signal. The sample and hold can sample input
signals in either single-ended or pseudo differential mode.
5.2 Input Op Amps
When driving the analog inputs with an op amp it is important
that the op amp settle within the allowed time. To achieve the
full sampling rate, the analog input should be driven with a
low impedance source (100 ) or a high-speed op amp such
as the LM6142. Higher impedance sources or slower op
amps can easily be accommodated by allowing more time
for the analog input to settle.
5.3 Source Resistance
The analog inputs of the ADC08831/2 look like a 13pF ca-
pacitor (C
switched between the selected “+” and “−” inputs during
each conversion cycle. Large external source resistors will
slow the settling of the inputs. It is important that the overall
RC time constants be short enough to allow the analog input
to completely settle.
and f
V
PEAK
cause
CLK
CM
IN
is its peak voltage value
is the frequency of the common-mode signal,
is the A/D clock frequency.
) in series with 300
conversion
1
⁄
2
errors.
of a clock period. The change
resistor (Ron). C
For
(Continued)
±
a
1µA over tem-
1
⁄
4
source re-
sinusoidal
LSB error
IN
gets
14
5.4 Board Layout Consideration, Grounding and
Bypassing:
The ADC08831/2 are easy to use with some board layout
consideration. They should be used with an analog ground
plane and single-point grounding techniques. The GND pin
should be tied directly to the ground plane.
The supply pin should be bypassed to the ground plane with
a surface mount or ceramic capacitor with leads as short as
possible. All analog inputs should be referenced directly to
the single-point ground. Digital inputs and outputs should be
shielded from and routed away from the reference and ana-
log circuitry.
6.0 OPTIONAL ADJUSTMENTS
6.1 Zero Error
The offset of the A/D does not require adjustment. If the mini-
mum analog input voltage value, V
zero offset can be done. The converter can be made to out-
put 0000 0000 digital code for this minimum input voltage by
biasing any V
the differential mode operation of the A/D.
The zero error of the A/D converter relates to the location of
the first riser of the transfer function and can be measured by
grounding the V
positive voltage to the V
ence between the actual DC input voltage which is neces-
sary to just cause an output digital code transition from 0000
0000 to 0000 0001 and the ideal
9.8mV for V
6.2 Full Scale
The full-scale adjustment can be made by applying a differ-
ential input voltage which is 1
analog full-scale voltage range and then adjusting the mag-
nitude of the V
tal output code which is just changing from 1111 1110 to 1111
1111.
6.3 Adjusting for an Arbitrary Analog Input
Voltage Range
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal
which does not go to ground), this new zero reference
should be properly adjusted first. A V
equals this desired zero reference plus
LSB is calculated for the desired analog span, using 1 LSB =
analog span/256) is applied to selected “+” input and the
zero reference voltage at the corresponding “−” input should
then be adjusted to just obtain the 00
sition.
The full-scale adjustment should be made [with the proper
V
put which is given by:
where:
and
(Both are ground referenced.)
IN
V
V
(−) voltage applied] by forcing a voltage to the V
MAX
MIN
= the low end (the offset zero) of the analog range.
= the high end of the analog input range
REF
IN
REF
IN
(−) input at this V
= 5.000V
input (or V
(−) input and applying a small magnitude
IN
DC
(+) input. Zero error is the differ-
).
CC
1
⁄
2
for the ADC08832) for a digi-
LSB down from the desired
IN(MIN)
1
⁄
2
IN(MIN)
HEX
LSB value (
IN
to 01
1
value. This utilizes
⁄
(+) voltage which
2
, is not ground a
LSB (where the
HEX
code tran-
1
⁄
2
IN
LSB =
(+) in-