XC3S100E-5TQ144C Xilinx Inc, XC3S100E-5TQ144C Datasheet - Page 99

• Manufacturer Part Number: XC3S100E-5TQ144C
• Description: FPGA Spartan®-3E Family 100K Gates 2160 Cells 657MHz 90nm (CMOS) Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc

Specifications of XC3S100E-5TQ144C

• Package: 144TQFP
• Family Name: Spartan®-3E
• Device Logic Cells: 2160
• Device Logic Units: 240
• Device System Gates: 100000
• Number Of Registers: 1920
• Maximum Internal Frequency: 657 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 108
• Ram Bits: 73728
• Re-programmability Support: Yes

The mode select pins, M[2:0], are sampled when the
FPGA’s INIT_B output goes High and must be at defined
logic levels during this time. After configuration, when the
FPGA’s DONE output goes High, the mode pins are avail-
able as full-featured user-I/O pins.
enable pull-up resistors on all user-I/O pins or High to dis-
able the pull-up resistors. The HSWAP control must remain
at a constant logic level throughout FPGA configuration.
After configuration, when the FPGA’s DONE output goes
High, the HSWAP pin is available as full-featured user-I/O
pin and is powered by the VCCO_0 supply.
DS312-2 (v3.8) August 26, 2009
Product Specification
P
Similarly, the FPGA’s HSWAP pin must be Low to
• Internal memory
• Disk drive
• Over network
• Over RF link
Configuration
Memory
Source
R
Download Host
Intelligent
•
•
•
•
Microcontroller
Processor
Tester
Computer
SERIAL_OUT
Recommend
open-drain
PROG_B
driver
VCC
GND
PROG_B
V
CLOCK
INIT_B
TMS
TDO
TCK
DONE
TDI
+2.5V
JTAG
Figure 63: Slave Serial Configuration
www.xilinx.com
Slave
Serial
Mode
P
‘1’
‘1’
‘1’
Voltage Compatibility
FPGA’s I/O Bank 2, supplied by the VCCO_2 supply input.
The VCCO_2 voltage can be 3.3V, 2.5V, or 1.8V to match
the requirements of the external host, ideally 2.5V. Using
3.3V or 1.8V requires additional design considerations as
the DONE and PROG_B pins are powered by the FPGA’s
2.5V V
tion of Spartan-3 FPGAs for additional information.
Daisy-Chaining
If the application requires multiple FPGAs with different con-
figurations, then configure the FPGAs using a daisy chain,
as
(M[2:0] = <1:1:1>) for all FPGAs in the daisy-chain. After
the lead FPGA is filled with its configuration data, the lead
FPGA passes configuration data via its DOUT output pin to
the next FPGA on the falling CCLK edge.
V
HSWAP
M2
M1
M0
CCLK
DIN
TDI
PROG_B
TMS
TCK
shown
Most Slave Serial interface signals are within the
CCAUX
Spartan-3E
VCCINT
FPGA
+1.2V
GND
in
supply. See XAPP453: The 3.3V Configura-
Figure
VCCAUX
VCCO_0
VCCO_2
INIT_B
DONE
DOUT
TDO
64.
Use
VCCO_0
+2.5V
V
Functional Description
Slave
V
DS312-2_54_082009
Serial
+2.5V
mode
99