89TTM553BL Integrated Device Technology (Idt), 89TTM553BL Datasheet - Page 4

• Manufacturer Part Number: 89TTM553BL
• Description: ATM Traffic Management 10Gbps 1.8V 960-Pin FCBGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 89TTM553BL

• Package: 960FCBGA
• Traffic Class: VBR
• Throughput: 10000 Mbps
• Typical Operating Supply Voltage: 1.8 V
• Minimum Operating Supply Voltage: 1.71 V
• Maximum Operating Supply Voltage: 1.89 V

89TTM553 Pin Description
89TTM553 Pin Description
89TTM553 Pin Description
89TTM553 Pin Description
IDT 89TTM553
In this data sheet, direction is indicated as follows: I for In, O for Out, B for Bi-directional, and P for power.
Note: Information in this section is subject to change. Contact your IDT FAE before making design decisions.
BLL_CLK_CP,
BLL_CLK_CN
BLL_CLK_KP,
BLL_CLK_KN
BLL_ADDR[21:0]
BLL_RD_N
BLL_DIN[17:0]
BLL_WR_N
BLL_DOUT[17:0]
BLL_VREF
BXT_CLK_CP,
BXT_CLK_CN
BXT_CLK_KP,
BXT_CLK_KN
BXT_ADDR[21:0]
BXT_RD_N
BXT_DIN[3:0]
Signal Name
Signal Name
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
0.75V
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
I/O Type
I/O Type
Table 2 Buffer Linked List Extension QDR SRAM (Part 1 of 2)
Table 1 Buffer Linked List QDR SRAM
Dir.
Dir.
—
O
O
O
O
O
O
O
O
I
I
I
I
4 of 30
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
Freq.
Freq.
—
BLL QDR SRAM input clock: This clock pair registers data
inputs on the rising edge of C and C#. All synchronous inputs
must meet setup and hold times around the clock rising
edges.
BLL QDR SRAM output clock: This clock pair times the control
outputs to the rising edge of K, and times the address and
data outputs to the rising edge of K and K#.
BLL QDR SRAM address outputs.
asserted, a read cycle is initiated to the external QDR SRAM
devices.
hold times around the rising edges of C and C# during read
operations
BLL QDR SRAM synchronous write output (active low): When
asserted, a write cycle is initiated to the external QDR SRAM
devices.
BLL QDR SRAM write data outputs: Output data is synchro-
nized to the K and K# during write operations
HSTL reference. Nominally V
inputs on the rising edge of C and C#. All synchronous inputs
must meet setup and hold times around the clock rising
edges.
trol outputs to the rising edge of K, and times the address and
data outputs to the rising edge of K and K#.
asserted, a read cycle is initiated to the external QDR SRAM
devices.
hold times around the rising edges of C and C# during read
operations
BLL QDR SRAM synchronous read output (active low): When
BLL QDR SRAM data inputs: Input data must meet setup and
BXT QDR SRAM input clock: This clock pair registers data
BXT QDR SRAM output clock: This clock pair times the con-
BXT QDR SRAM address outputs.
BXT QDR SRAM synchronous read output (active low): When
BXT QDR SRAM data inputs: Input data must meet setup and
Remarks
Remarks
DDQ
/ 2, so connect to 0.75 V
March 3, 2005