CS5102A-JL Cirrus Logic Inc, CS5102A-JL Datasheet - Page 16

• Manufacturer Part Number: CS5102A-JL
• Description: ADC Single SAR 20KSPS 16-Bit Serial 28-Pin PLCC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5102A-JL

• Package: 28PLCC
• Resolution: 16 Bit
• Sampling Rate: 20 KSPS
• Architecture: SAR
• Number Of Adcs: 1
• Number Of Analog Inputs: 2
• Digital Interface Type: Serial
• Input Type: Voltage
• Signal To Noise Ratio: 90(Typ) dB
• Polarity Of Input Voltage: Unipolar|Bipolar

Output Mode Control
The CS5101A and CS5102A can be configured
in three different output modes, as well as an in-
ternal, synchronous loop-back mode. This allows
great flexibility for design into a wide variety of
systems. The operating mode is selected by set-
ting the states of the SCKMOD and OUTMOD
pins. In all modes, data is output on SDATA,
starting with the MSB. Each subsequent data bit
is updated on the falling edge of SCLK.
When SCKMOD is high, SCLK is an input, al-
lowing the data to be clocked out with an
external serial clock at rates up to 5 MHz. Addi-
tional clock edges after #16 will clock out logic
’1’s on SDATA. Tying SCKMOD low reconfig-
ures SCLK as an output, and the converter clocks
CLKIN (i)
HOLD (i)
CH1/2 (i)
Internal
Status
SCLK (i)
SDATA (o)
SSH/SDL (o)
TRK1 (o)
TRK2 (o)
16
0
D15
4
Converting Ch. 2
D14
8
MODE
SSC
PDT
RBT
FRN
D1 D0 (Ch. 1)
60
Figure 3. Pipelined Data Transmission Mode (PDT)
SCKMOD
64
1
1
0
0
68
Table 2. Serial Output Modes
Tracking Ch. 1
72
OUTMOD
76
1
0
1
0
0
out each bit as it’s determined during the conver-
sion process, at a rate of 1/4 the master clock
speed. Table 2 shows an overview of the different
states of SCKMOD and OUTMOD, and the cor-
responding output modes.
Pipelined Data Transmission (PDT)
PDT mode is selected by tying both SCKMOD
and OUTMOD high. In PDT mode, the SCLK
pin is an input. Data is registered during conver-
sion, and output during the following conversion
cycle. HOLD must be brought low, initiating an-
other conversion, before data from the previous
conversion is available on SDATA. If all the data
has not been clocked out before the next falling
edge of HOLD, the old data will be lost
(Figure 3).
D15
Output
Output
SCLK
Input
Input
4
Converting Ch. 1
D14
8
CH1/2
Output
Input
Input
Input
D1
60
CS5101A CS5102A
D0 (Ch. 2)
64
HOLD
Input
Input
Input
X
68
Tracking Ch. 2
72
76
DS45F2
0
D15