XC3S2000-4FG676C Xilinx Inc, XC3S2000-4FG676C Datasheet - Page 102

• Manufacturer Part Number: XC3S2000-4FG676C
• Description: FPGA Spartan®-3 Family 2M Gates 46080 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA
• Manufacturer: Xilinx Inc

Specifications of XC3S2000-4FG676C

• Package: 676FBGA
• Family Name: Spartan®-3
• Device Logic Units: 46080
• Device System Gates: 2000000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 489
• Ram Bits: 737280

Spartan-3 FPGA Family: Pinout Descriptions
Table 69: Spartan-3 FPGA Pin Definitions (Continued)
102
IO_Lxxy_#/INIT_B
DCI: Digitally Controlled Impedance reference resistor input pins
IO_Lxxy_#/VRN_# or
IO/VRN_#
IO_Lxxy_#/VRP_# or
IO/VRP_#
GCLK: Global clock buffer inputs
IO_Lxxy_#/GCLK0,
IO_Lxxy_#/GCLK1,
IO_Lxxy_#/GCLK2,
IO_Lxxy_#/GCLK3,
IO_Lxxy_#/GCLK4,
IO_Lxxy_#/GCLK5,
IO_Lxxy_#/GCLK6,
IO_Lxxy_#/GCLK7
VREF: I/O bank input reference voltage pins
IO_Lxxy_#/VREF_#
or
IO/VREF_#
CONFIG: Dedicated configuration pins (pull-up resistor to VCCAUX always active during configuration, regardless of
HSWAP_EN pin)
CCLK
PROG_B
Pin Name
Bidirectional (open-drain)
during configuration
User I/O after configuration
Input when using DCI
Otherwise, same as I/O
Input when using DCI
Otherwise, same as I/O
Input if connected to global
clock buffers
Otherwise, same as I/O
Voltage supply input when
VREF pins are used within a
bank.
Otherwise, same as I/O
Input in Slave configuration
modes
Output in Master
configuration modes
Input
Direction
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Initializing Configuration Memory/Detected Configuration Error:
When Low, this pin indicates that configuration memory is being
cleared. When held Low, this pin delays the start of configuration.
After this pin is released or configuration memory is cleared, the
pin goes High. During configuration, a Low on this output indicates
that a configuration data error occurred. This pin always has an
internal pull-up resistor to VCCO_4 or VCCO_BOTTOM during
configuration, regardless of the HSWAP_EN pin. This pin
becomes a user I/O after configuration.
DCI Reference Resistor for NMOS I/O Transistor (per bank):
If using DCI, a 1% precision impedance-matching resistor is
connected between this pin and the VCCO supply for this bank.
Otherwise, this pin is a user I/O.
DCI Reference Resistor for PMOS I/O Transistor (per bank):
If using DCI, a 1% precision impedance-matching resistor is
connected between this pin and the ground supply. Otherwise, this
pin is a user I/O.
Global Buffer Input:
Direct input to a low-skew global clock buffer. If not connected to a
global clock buffer, this pin is a user I/O.
Input Buffer Reference Voltage for Special I/O Standards (per
bank):
If required to support special I/O standards, all the VREF pins
within a bank connect to a input threshold voltage source.
If not used as input reference voltage pins, these pins are available
as individual user-I/O pins.
Configuration Clock:
The configuration clock signal synchronizes configuration data.
This pin has an internal pull-up resistor to VCCAUX during
configuration.
Program/Configure Device:
Active Low asynchronous reset to configuration logic. Asserting
PROG_B Low for an extended period delays the configuration
process. This pin has an internal pull-up resistor to VCCAUX
during configuration.
Description
DS099-4 (v2.5) December 4, 2009
Product Specification
R