AD9101AR Analog Devices Inc, AD9101AR Datasheet - Page 4

• Manufacturer Part Number: AD9101AR
• Description: Sample and Hold 1-CH 0.016us 20-Pin SOIC W
• Manufacturer: Analog Devices Inc

Specifications of AD9101AR

• Package: 20SOIC W
• Acquisition Time: 0.016 us
• Number Of S/h: 1
• Operating Supply Voltage: -5.2/5 V

AD9101
Acquisition Time is the amount of time it takes the AD9101
to reacquire the analog input when switching from hold to track
mode. The interval starts at the 50% clock transition point and
ends when the input signal is reacquired to within a specified
error band at the hold capacitor.
Aperture Delay establishes when the input signal is actually
sampled. It is the time difference between the analog propaga-
tion delay of the front-end buffer and the control switch delay
time (the time from the hold command transition to when the
switch is opened). For the AD9101, this is a negative value,
meaning that the analog delay is longer than the switch delay.
Aperture Jitter is the random variation in the aperture delay.
This is measured in ps-rms and is manifested as phase noise on
the held signal.
Droop Rate is the change in output voltage as a function of
time (dV/dt). It is measured at the AD9101 output with the de-
vice in hold mode and the input held at a specified dc value; the
measurement starts immediately after the T/H switches from
track to hold.
Feedthrough Rejection is the ratio of the output signal to the
input signal when in hold mode. This is a measure of how well
the switch isolates the input signal from feeding through to the
output.
AND AMPLIFIER OUTPUT SIGNAL
SAMPLER OUTPUT SIGNAL (x 4)
INPUT (x 4)
ANALOG
INPUTS
CLOCK
+2V
+2V
-2V
-2V
"1"
"0"
0V
0V
HOLD TO TRACK
SWITCH DELAY
TIME (1.5 ns)
"HOLD"
CLOCK
Timing Diagram (500 ps/div)
–4–
ACQUISITION
TIME (SEE
Hold-to-Track Switch Delay is the time delay from the track
command to the point when the output starts to change to ac-
quire a new signal level.
Pedestal Offset is the offset voltage measured immediately af-
ter the AD9101 is switched from track to hold with the input
held at zero volts. It manifests itself as a dc offset during the
hold time.
Sampling Bandwidth is the –3 dB frequency response from
the input to the hold capacitor under sampling conditions. It is
greater than the tracking bandwidth because it does not include
the bandwidth of the output amplifier which is optimized for
settling time rather than bandwidth.
Track-to-Hold Settling Time is the time necessary for the
track to hold switching transient to settle to within 4 mV of its
final value.
Track-to-Hold Switching Transient is the maximum peak
switch induced transient voltage which appears at the AD9101
output when it is switched from track to hold.
TEXT)
"TRACK"
CLOCK
AMPLIFIER OUTPUT
HOLD CAPACITOR
OBSERVED AT
OBSERVED AT
LEVEL HELD
VOLTAGE
TRACK TO
SETTLING
HOLD
(4 ns)
APERTURE
(–0.25 ns)
DELAY
"HOLD"
CLOCK
REV. 0