ST52T440F3M6 STMicroelectronics, ST52T440F3M6 Datasheet - Page 22

• Manufacturer Part Number: ST52T440F3M6
• Description: MCU 8-Bit ST52 CISC 8KB EPROM 5V 20-Pin SO
• Manufacturer: STMicroelectronics

Specifications of ST52T440F3M6

• Package: 20SO
• Family Name: ST52
• Maximum Speed: 20 MHz
• Ram Size: 256 Byte
• Program Memory Size: 8 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 13
• On-chip Adc: 6-chx12-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 1

ST52T400/T440/E440/T441
2.2.1 Ram and Stack.
RAM consists of 128 (G0/G1/F0/F1 types) or 256
(G2/G3/F2/F3 types) general purpose 8-bit regis-
ters.
All the registers in RAM can be specified by using
a decimal address, e.g. 0 identifies the first regis-
ter of RAM.
To read or write in the RAM registers, the LOAD
instructions must be used (see Table 2.5).
When the instructions like Interrupt request or
CALL are executed, a STACK is used to push the
PC. The STACK is push directly in the RAM. For
each level of stack 2 bytes of RAM are used. The
values of this stack are stored from the last RAM
register (address 255). The maximum level of
stack must be less than 128. When a subroutine
call or interrupt request occurs, the contents of
each level is shifted into the next level while the
content of the PC is shifted into the first level.
When a subroutine or interrupt return occurs (RET
or RETI instructions), the first level register is
shifted back into the PC and the value of each
level is popped back into the previous level. These
operating modes are illustrated in Figure 2.5.
Figure 2.5 Stack Operation
22/94
WHEN RETI OR RET
OCCURS
REG 252
REG 253
REG 254
REG 255
REG 0
REG 1
REG 2
REG 3
REG 4
REG 5
PROGRAM COUNTER
STACK LEVEL n
..........................
STACK LEVEL 2
STACK LEVEL 1
RAM
2.2.2 Input Registers Bench.
The Input Registers (IR) bench consists of 20 8-bit
registers containing data deriving from the periph-
erals and parallel ports.
All the registers can be specified by using a deci-
mal address, e.g. 0 identifies the first register of
the IR.
The assembler instruction: LDRI reg,inp_teg loads
the value in the inp IR to the register (RAM loca-
tion) identified by the address reg.
The first input register is dedicated to store the
value of the stack pointer. The next 12 registers of
the IR are dedicated to the 6 (for ST52X440G/
441G) or the 4 converted values (for ST52X440F/
441F) in case of converted values coming from
the Analog Comparator (in ST52x400 devices
these registers are not used). Each of these val-
ues are stored on two bytes because of the reso-
lution of the A/D conversion process. The last 7
registers contain data from the I/O ports and
PWM/Timers. Table 2.1 summarizes the IR
address and the relative peripheral. In order to
simplify the concept a mnemonic name is
assigned to the registers. The same name is used
in VISUAL FIVE development tools.
Stack
Pointer
INTERRUPT REQ.
WHEN CALL OR
OCCURS