ST52T440F3M6 STMicroelectronics, ST52T440F3M6 Datasheet - Page 30

• Manufacturer Part Number: ST52T440F3M6
• Description: MCU 8-Bit ST52 CISC 8KB EPROM 5V 20-Pin SO
• Manufacturer: STMicroelectronics

Specifications of ST52T440F3M6

• Package: 20SO
• Family Name: ST52
• Maximum Speed: 20 MHz
• Ram Size: 256 Byte
• Program Memory Size: 8 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 13
• On-chip Adc: 6-chx12-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 1

ST52T400/T440/E440/T441
2.4 Arithmetic Logic Unit
ST52x400/440/441 supplies 46 instructions that
perform computations and control the device.
Computational time required for each instruction
consists of one clock pulse for each Cycle plus 2
clock pulses for the decoding phase. Total compu-
tation time for each instruction is reported in Table
2.5
The ALU of the ST52x400/440/441 can perform
multiplication (MULT) and division (DIV). Multipli-
cation is performed by using 8 bit operands stor-
ing the result in 2 registers (16 bit values).
Division is performed between a 16 bit dividend
and an 8 bit divider, the result and the remainder
are stored in two 8-bit registers.
WARNING: If the LSB of the multiplication result
is 0, the Zero flag is set although the result is not
0.
2.4.1 Addressing Modes.
ST52x400/440/441 instructions allow the following
addressing modes:
Inherent: this instruction type does not require an
operand because the opcode specifies all the
information necessary to carry out the instruction.
Examples: NOP, RET.
Immediate: these instructions have an operand as
a source immediate value. Examples: LDRC,
Table 2.5 Arithmetic & Logic Instruction Set
30/94
Mnemonic
PGSET
LDCE
LDCR
LDPR
LDRC
LDRE
LDRE
LDRR
LDFR
LDPE
LDPE
LDRI
LDRE (regx),(regy)
LDCE confx,memx
LDFR fuzzyx,regx
LDRE regx,memx
LDPE outx,memx
LDPE outx,(regx)
LDRC confx,regx
LDRC regx,const
LDRR regx, regy
LDPR outx,regx
LDRI regx,inpx
PGSET const
Instruction
Load Instructions
Bytes
3
3
3
3
3
3
3
3
3
3
3
2
PGSET.
Direct: the operands of these instructions are
specified with the direct addresses. The operands
can refer, according to the opcode, to addresses
belonging to the different addressing spaces.
Example: SUB, LDRE.
Indirect: data addresses that are required are
found in the locations specified as operands. Both
source and/or destination operands can be
addressed indirectly. The operands can refer,
(according to the opcode) to addresses belonging
to different addressing spaces. Examples: LDRE
(reg1),(reg2).
2.4.2 Instruction Types.
ST FIVE supplies the following instruction types:
The instructions are listed in Table 2.5, Table 2.6
and Table 2.7.
Load Instructions
Arithmetic and Logic Instructions
Jump Instructions
Interrupt Management Instructions
Control Instructions
Cycles
17
14
14
17
17
14
14
16
18
15
16
9
Z
-
-
-
-
-
-
-
-
-
-
-
-
S
-
-
-
-
-
-
-
-
-
-
-
-
C
-
-
-
-
-
-
-
-
-
-
-
-