AT32UC3C2512C-A2ZR Atmel, AT32UC3C2512C-A2ZR Datasheet - Page 69
AT32UC3C2512C-A2ZR
Manufacturer Part Number
AT32UC3C2512C-A2ZR
Description
Microcontrollers (MCU) 512KB FL,-40/125oC AUTO
Manufacturer
Atmel
Datasheet
1.AT32UC3C1512C-AZR.pdf
(106 pages)
Specifications of AT32UC3C2512C-A2ZR
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7.9
7.9.1
Table 7-43.
9166BS–AVR-02/11
Parameter
Startup time from power-up, using
regulator
Startup time from reset release
Wake-up
Timing Characteristics
Startup, Reset, and Wake-up Timing
Maximum Reset and Wake-up Timing
Idle
Frozen
Standby
Stop
Deepstop
Static
The startup, reset, and wake-up timings are calculated using the following formula:
Where
clock the startup time of the oscillator,
stop, deepstop, and static sleep modes. Please refer to the source for the CPU clock in the
”Oscillator Characteristics” on page 56
t
t
CPU
=
t
CONST
is the period of the CPU clock. If another clock source than RCSYS is selected as CPU
t
CONST
VDDIN_5 rising (10 mV/ms)
Time from V
the decode stage of CPU. VDDCORE is supplied by
the internal regulator.
Time from releasing a reset source (except POR,
BOD18, and BOD33) to the first instruction entering
the decode stage of CPU.
From wake-up event to the first instruction entering
the decode stage of the CPU.
Measuring
+
N
and
CPU
×
N
CPU
VDDIN_5
t
CPU
are found in
=0 to the first instruction entering
for more details about oscillator startup times.
t
OSCSTART
Table
7-43.
, must be added to the wake-up time in the
t
CONST
Max
268+
268+
268+
is the delay relative to RCSYS,
t
CONST
t
t
t
2600
1240
OSCSTART
OSCSTART
OSCSTART
268
268
0
(in µs)
AT32UC3C
Max
209
209
212
212
212
N
19
0
0
CPU
69
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