SAF-C167CS-LM CA+ Infineon Technologies, SAF-C167CS-LM CA+ Datasheet - Page 13

• Manufacturer Part Number: SAF-C167CS-LM CA+
• Description: Microcontrollers (MCU) 16BIT SNGL CHIP 5V 25MHz ROM less
• Manufacturer: Infineon Technologies

Specifications of SAF-C167CS-LM CA+

• Data Bus Width: 16 bit
• Program Memory Type: ROMLess
• Data Ram Size: 11 KB
• Interface Type: ASC, CAN, SSC
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: MQFP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Packages: PG-MQFP-144
• Max Clock Frequency: 25.0 MHz
• Sram (incl. Cache): 11.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 24
• Program Memory: 0.0 KByte
• Lead Free Status / Rohs Status: Details
• Other names: F167CSLMCAZNT

Table 2
Symbol Pin
P4
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
RD
WR/
WRL
READY 97
Data Sheet
Num.
85
86
87
88
89
90
91
92
95
96
Pin Definitions and Functions (cont’d)
Input
Outp.
IO
O
O
O
O
O
I
O
I
O
O
O
O
I
O
I
O
O
I
Function
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. The Port 4 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 4
is selectable (TTL or special).
Port 4 can be used to output the segment address lines and
for serial interface lines:
A16
A17
A18
A19
A20
CAN2_RxD CAN 2 Receive Data Input
A21
CAN1_RxD CAN 1 Receive Data Input
A22
CAN1_TxD CAN 1 Transmit Data Output,
CAN2_TxD CAN 2 Transmit Data Output
A23
CAN1_RxD CAN 1 Receive Data Input,
CAN2_TxD CAN 2 Transmit Data Output,
CAN2_RxD CAN 2 Receive Data Input
External Memory Read Strobe. RD is activated for every
external instruction or data read access.
External Memory Write Strobe. In WR-mode this pin is
activated for every external data write access. In WRL-mode
this pin is activated for low byte data write accesses on a
16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in register SYSCON for mode selection.
Ready Input. When the Ready function is enabled, a high
level at this pin during an external memory access will force
the insertion of memory cycle time waitstates until the pin
returns to a low level.
An internal pullup device will hold this pin high when nothing
is driving it.
Least Significant Segment Address Line
Segment Address Line
Segment Address Line
Segment Address Line
Segment Address Line,
Segment Address Line,
Segment Address Line,
Most Significant Segment Address Line,
9
1)
C167CS-4R
V2.2, 2001-08
C167CS-L