IS42S16320B-7BLI ISSI, Integrated Silicon Solution Inc, IS42S16320B-7BLI Datasheet - Page 25

• Manufacturer Part Number: IS42S16320B-7BLI
• Description: DRAM 512M (32Mx16) 143MHz Industrial Temp
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS42S16320B-7BLI

• Data Bus Width: 16 bit
• Package / Case: WBGA-54
• Memory Size: 512 Mbit
• Maximum Clock Frequency: 143 MHz
• Access Time: 6.5 ns, 5.4 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 130 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Details

IS42S86400B, IS42S16320B
BURST LENGTH
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown in
MODE REGISTER DEFINITION. The burst length deter-
mines the maximum number of column locations that can
be accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page
burst is available for the sequential type. The full-page
burst is used in conjunction with the BURST TERMINATE
command to generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.All
accesses for that burst take place within this block, mean-
ing that the burst will wrap within the block if a boundary
BURST DEFINITION
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00F
08/11/08
Length
Burst
Page
Full
(y)
2
4
8
n = A0-A9, A11 (x8)
n = A0-A9 (x16)
(location 0-y)
A 2
0
0
0
0
1
1
1
1
Starting Column
Address
A 1
A 1
0
0
1
1
0
0
1
0
0
1
1
1
A 0
A 0
A 0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
Type = Sequential
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
…Cn - 1,
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
Cn…
0-1
1-0
Burst Type
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
is reached. The block is uniquely selected by A1-A9 (x16)
or A1-A9, A11 (x8) when the burst length is set to two; by
A2-A9 (x16) or A1-A9, A11 (x8) when the burst length is
set to four; and by A3-A9 (x16) or A1-A9, A11 (x8) when
the burst length is set to eight. The remaining (least sig-
nificant) address bit(s) is (are) used to select the starting
location within the block. Full-page bursts wrap within the
page if the boundary is reached.
the burst length, the burst type and the starting column
address, as shown in BURST DEFINITION table.
Order of Accesses Within a Burst
Type = Interleaved
0-1-2-3-4-5-6-7
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
1-0-3-2-5-4-7-6
Not Supported
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0
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