LFSC3GA15E-5FN256C Lattice, LFSC3GA15E-5FN256C Datasheet - Page 13

• Manufacturer Part Number: LFSC3GA15E-5FN256C
• Description: IC FPGA 15.2KLUTS 256FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-5FN256C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-7. Edge Clock Resources
Precision Clock Divider
Each set of edge clocks has four high-speed dividers associated with it. These are intended for generating a slower
speed system clock from the high-speed edge clock. The block operates in a DIV2 or DIV4 mode and maintains a
known phase relationship between the divided down clock and high-speed clock based on the release of its reset
signal. The clock dividers can be fed from selected PIOs, PLLs and routing. The clock divider outputs serve as pri-
mary clock sources. This circuit also generates an edge local set/reset (ELSR) signal which is fed to the PIOs via
the edge clock network and is used for the rest of the I/O gearing logic.
Figure 2-8. Clock Divider Circuit
Dynamic Clock Select (DCS)
The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and
outputs a clock signal without any glitches or runt pulses. This is achieved irrespective of where the select signal is
Clock derived
from selected
PIOs, PLLs and
routing
LSR
SERDES
Register chain to synchronize LSR to clock input
Bank 5
S/R
Bank 1
2-9
S/R
Edge clock
Bank 4
S/R
SERDES
LatticeSC/M Family Data Sheet
S/R
ELSR
Divided clock
Architecture