LFSC3GA15E-5FN256C Lattice, LFSC3GA15E-5FN256C Datasheet - Page 41

• Manufacturer Part Number: LFSC3GA15E-5FN256C
• Description: IC FPGA 15.2KLUTS 256FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-5FN256C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-31. LatticeSC System Bus Interfaces
Several interfaces exist between the System Bus and other FPGA elements. The MPI interface acts as a bridge
between the external microprocessor bus and System Bus. The MPI may work in an independent clock domain
from the System Bus if the System Bus clock is not sourced from the external microprocessor clock. Pipelined
operation allows high-speed memory interface to the EBR and peripheral access without the requirement for addi-
tional cycles on the bus. Burst transfers allow optimal use of the memory interface by giving advance information of
the nature of the transfers.
Details for the majority of the peripherals can be found in the associated technical documentation, see details at
the end of this data sheet. Additional details of the MPI are provided below.
Microprocessor Interface (MPI)
The LatticeSC family devices have a dedicated synchronous MPI function block. The MPI is programmable to oper-
ate with PowerPC/PowerQUICC MPC860/MPC8260 series microprocessors. The MPI implements an 8-, 16-, or
32-bit interface with 1-bit, 2-bit, or 4-bit parity to the host processor (PowerPC) that can be used for configuration
and read-back of the FPGA as well as for user-defined data processing and general monitoring of FPGA functions.
The control portion of the MPI is available following power-up of the FPGA if the mode pins specify MPI mode, even
if the FPGA is not yet configured. The width of the data port is selectable among 8-, 16-, or 32-bit and the parity bus
can be 1-, 2-, or 4-bit. In configuration mode the data and parity bus width are related to the state of the M[0:3]
mode pins. For post-configuration use, the MPI must be included in the configuration bit stream by using an MPI
library element in your design from the ispLEVER primitive library, or by setting the bit of the MPI configuration con-
trol register prior to the start of configuration. The user can also enable and disable the parity bus through the con-
figuration bit stream. These pads can be used as general I/O when they are not needed for MPI use.
The MPI block also provides the capability to interface directly to the FPGA fabric with a databus after configura-
tion.The bus protocol is still handled by the MPI block but the direct FPGA access allows high-speed block data
transfers such as DMA transactions. Figure 2-32 shows one of the ways a PowerPC is connected to MPI.
(Direct Access
from MPI)
(MASTER)
DFA
MPI
USER LOGIC)
(PLL, DLL,
PCS (LEFT, RIGHT
and INTER-QUAD)
SMI
(SLAVE)
System Bus
2-37
(MASTER)
CONFIG
EBR INIT
(WRITE)
STATUS and
(SYS REG)
CONFIG
LatticeSC/M Family Data Sheet
(MASTER)
UMI
(SLAVE)
USI
Architecture