LFSC3GA15E-6FN256C Lattice, LFSC3GA15E-6FN256C Datasheet - Page 27

• Manufacturer Part Number: LFSC3GA15E-6FN256C
• Description: IC FPGA 15.2KLUTS 256FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-6FN256C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 2-6. Input/Output/Tristate Gearing Resource Rules
Control Logic Block
The control logic block allows the modification of control signals selected by the routing before they are used in the
PIO. It can optionally invert all signals passing through it except the Global Set/Reset. Global Set/Reset can be
enabled or disabled. It can route either the edge clock or the clock to the high-speed clock nets. The clock provided
to the PIO by routing is used as the slow-speed clocks. In addition this block contains delays that can be inserted in
the clock nets to enable Lattice’s unique cycle boosting capability.
Update Block
The update block is used to generate the POS update and NEG update signals used by the DDR/Shift register
blocks within the PIO. Note the update block is only required in shift modes. This is required in order to do the high
speed to low speed handoff. One of these update signals is also selected and output from the PIC as the signal
UPDATE. It consists of a shift chain that operates off either the high-speed input or output clock. The values of each
register in the chain are set or reset depending on the desired mode of operation. The set/reset signal is generated
from either the edge reset ELSR or the local reset LSR. These signals are optionally inverted by the Control Logic
Block and provided to the update block as ELSRUP and LSRUP. The Lattice design tools automatically configure
and connect the update block when one of the DDR or shift register primitives is used.
Figure 2-25. Update Block
PURESPEED I/O Buffer
Each I/O is associated with a flexible buffer referred to as PURESPEED I/O buffer. These buffers are arranged
around the periphery of the device in seven groups referred to as Banks. The PURESPEED I/O buffers allow users
to implement the wide variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL,
LVDS and LVPECL. The availability of programmable on-chip termination for both input and output use, further
enhances the utility of these buffers.
HCLKUP
ESLRUP
LCLKUP
Note: Pin can still be used without I/O logic.
LSRUP
PIO
C
D
A
B
x1
✓
✓
✓
✓
Input/Output Logic
No I/O Logic No I/O Logic
No I/O Logic No I/O Logic
x2
✓
✓
2-23
No I/O Logic
x4
✓
÷1/2/4
LatticeSC/M Family Data Sheet
x1
✓
✓
✓
✓
Tri-State/Bidi
UPDATE
POS Update
NEG Update
x2/x4
N/A
N/A
N/A
N/A
Architecture