LFSC3GA15E-6FN256C Lattice, LFSC3GA15E-6FN256C Datasheet - Page 52

• Manufacturer Part Number: LFSC3GA15E-6FN256C
• Description: IC FPGA 15.2KLUTS 256FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-6FN256C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Differential HSTL and SSTL
Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow-
able single-ended output classes (class I and class II) are supported in this mode.
MLVDS
The LatticeSC devices support the MLVDS standard. This industry standard is emulated using controlled imped-
ance complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs.
MLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The
scheme shown in Figure 3-1 is one possible solution for bi-directional multi-point differential signals.
Figure 3-1. MLVDS Multi-Point Output Example
Table 3-1. MLVDS DC Conditions
50
50
2.5V
2.5V
+
+
-
-
Z
R
R
V
V
V
V
I
1. For input buffer, see LVDS table.
DC
OUT
OH
OL
OD
TLEFT
TRIGHT
CM
Symbol
50-70 ohms, +/- 1%
2.5V
50
Heavily loaded backplane, effective Zo ~ 50 to 70 ohms differential
Over Recommended Operating Conditions
Output impedance
Left end termination
Right end termination
Output high voltage
Output low voltage
Output differential voltage
Output common mode voltage
DC output current
1
2.5V
50
Description
+
-
3-8
. . .
. . .
2.5V
Zo = 50
50
1.50
1.00
0.50
1.25
20.0
50
50
50
Nominal
DC and Switching Characteristics
50-70 ohms, +/- 1%
2.5V
LatticeSC/M Family Data Sheet
Zo = 70
1.575
0.925
50
0.65
1.25
18.5
50
70
70
+
Units
ohm
ohm
ohm
mA
-
V
V
V
V
2.5V
2.5V
+
-
50
50