PIC16LF1938-I/MV Microchip Technology, PIC16LF1938-I/MV Datasheet - Page 215

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PIC16LF1938-I/MV

Manufacturer Part Number
PIC16LF1938-I/MV
Description
IC MCU 8BIT 28KB FLASH 28UQFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet

Specifications of PIC16LF1938-I/MV

Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
28KB (16K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-UFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
23.3.7
In Sleep mode, the TMRx register will not increment
and the state of the module will not change. If the CCPx
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMRx will continue from its
previous state.
23.3.8
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 5.0 “Oscillator Module (With Fail-Safe
Clock Monitor)”
23.3.9
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
TABLE 23-8:
 2011 Microchip Technology Inc.
APFCON
CCPxCON
CCPTMRS0
CCPTMRS1
INTCON
PIE1
PIE2
PIE3
PIR1
PIR2
PIR3
PRx
TxCON
TMRx
TRISA
TRISB
TRISC
TRISD
TRISE
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.
Note 1:
Name
(2)
2:
3:
*
Applies to ECCP modules only.
These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’.
Unimplemented, read as ‘1’.
Page provides register information.
OPERATION IN SLEEP MODE
CHANGES IN SYSTEM CLOCK
FREQUENCY
EFFECTS OF RESET
Timer2/4/6 Period Register
Timer2/4/6 Module Register
TMR1GIE
TMR1GIF
TRISA7
TRISB7
TRISC7
TRISD7
OSFIE
OSFIF
Bit 7
GIE
for additional details.
C4TSEL<1:0>
SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM
PxM<1:0>
CCP3SEL
CCP5IE
CCP5IF
TRISC6
TRISD6
TRISA6
TRISB6
PEIE
ADIE
C2IE
ADIF
Bit 6
(1)
C2IF
T1GSEL
TMR0IE
CCP4IE
CCP4IF
TRISA5
TRISB5
TRISC5
TRISD5
RCIE
RCIF
Bit 5
C1IE
C1IF
TxOUTPS<3:0>
C3TSEL<1:0>
DCxB<1:0>
P2BSEL
CCP3IE
CCP3IF
TRISA4
TRISB4
TRISC4
TRISD4
Preliminary
Bit 4
INTE
TXIE
EEIE
TXIF
EEIF
SRNQSEL C2OUTSEL
TMR6IE
TMR6IF
TRISA3
TRISB3
TRISC3
TRISD3
SSPIE
BCLIE
SSPIF
BCLIF
IOCIE
23.3.10
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see
more information.
Bit 3
C2TSEL<1:0>
(3)
TRISE2
TMRxON
TMR0IF
CCP1IE
CCP1IF
TRISC2
TRISD2
TRISA2
TRISB2
LCDIE
LCDIF
Section 12.1 “Alternate Pin Function”
PIC16(L)F1938/9
ALTERNATE PIN LOCATIONS
Bit 2
CCPxM<3:0>
(2)
TRISE1
TMR2IE
TMR4IE
TMR2IF
TMR4IF
TRISA1
TRISB1
TRISC1
TRISD1
SSSEL
Bit 1
INTF
C1TSEL<1:0>
C5TSEL<1:0>
TxCKPS<:0>1
(2)
CCP2SEL
TRISE0
TMR1IE
CCP2IE
TMR1IF
CCP2IF
TRISA0
TRISB0
TRISC0
TRISD0
IOCIF
Bit 0
DS41574A-page 215
(2)
Register
on Page
203*
127
230
231
232
100
205
203
129
134
138
141
144
94
95
96
97
98
99
for

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