PIC16LF1938-I/MV Microchip Technology, PIC16LF1938-I/MV Datasheet - Page 38
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PIC16LF1938-I/MV
Manufacturer Part Number
PIC16LF1938-I/MV
Description
IC MCU 8BIT 28KB FLASH 28UQFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16LF1938-IMV.pdf
(452 pages)
Specifications of PIC16LF1938-I/MV
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
28KB (16K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-UFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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PIC16(L)F1938/9
TABLE 3-10:
DS41574A-page 38
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
Legend:
Note
Address
Bank 2
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
(1, 2)
(2)
1:
2:
3:
4:
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
LATA
LATB
LATC
LATD
LATE
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
FVRCON
DACCON0
DACCON1
SRCON0
SRCON1
—
APFCON
—
—
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
These registers can be addressed from any bank.
These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’.
Unimplemented, read as ‘1’.
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR0H/FSR0L to Address Data Memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to Address Data Memory
(not a physical register)
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
Working Register
PORTA Data Latch
PORTB Data Latch
PORTC Data Latch
PORTD Data Latch
Unimplemented
Unimplemented
Unimplemented
SBOREN
C1INTP
C2INTP
FVREN
DACEN
SRSPE
SRLEN
C1ON
C2ON
Bit 7
GIE
—
—
—
—
—
---
—
Write Buffer for the upper 7 bits of the Program Counter
CCP3SEL
SRSCKE
FVRRDY
DACLPS
SRCLK2
C1INTN
C2INTN
C1OUT
C2OUT
PEIE
Bit 6
—
—
—
—
—
---
C1PCH1
C2PCH1
SRSC2E
SRCLK1
T1GSEL
TMR0IE
DACOE
C1OE
C2OE
TSEN
Bit 5
—
—
—
—
—
---
Preliminary
SRSC1E
C1PCH0
C2PCH0
SRCLK0
P2BSEL
TSRNG
C1POL
C2POL
INTE
Bit 4
TO
—
—
—
---
CDAFVR1
SRNQSEL
SRQEN
SRRPE
IOCIE
Bit 3
PD
—
—
—
—
—
—
—
DACPSS<1:0>
DACR<4:0>
BSR<4:0>
C2OUTSEL
CDAFVR0
SRNQEN
SRRCKE
LATE2
TMR0IF
C1SP
C2SP
Bit 2
—
—
—
—
Z
(3)
MC2OUT
SRRC2E
LATE1
C1HYS
C2HYS
SSSEL
SRPS
2011 Microchip Technology Inc.
Bit 1
INTF
DC
—
---
C1NCH<1:0>
C2NCH<1:0>
ADFVR<1:0>
(3)
CCP2SEL -000 0000 -000 0000
MC1OUT ---- --00 ---- --00
BORRDY 1--- ---q u--- ---u
C1SYNC 0000 -100 0000 -100
C2SYNC 0000 -100 0000 -100
DACNSS 000- 00-0 000- 00-0
SRRC1E 0000 0000 0000 0000
LATE0
IOCIF
SRPR
Bit 0
C
(3)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
0000 --00 0000 --00
0000 --00 0000 --00
0q00 0000 0q00 0000
---0 0000 ---0 0000
0000 0000 0000 0000
POR, BOR
Value on
—
—
—
Value on all
Resets
other
—
—
—
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