PIC18F1220-H/ML Microchip Technology, PIC18F1220-H/ML Datasheet - Page 120
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F1220-H/ML
Manufacturer Part Number
PIC18F1220-H/ML
Description
IC MCU 8BIT 4KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F1220-ISO.pdf
(308 pages)
Specifications of PIC18F1220-H/ML
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
28-VQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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PIC18F1220/1320
FIGURE 15-2:
TABLE 15-3:
DS39605F-page 118
INTCON
PIR1
PIE1
IPR1
TRISB
TMR1L
TMR1H
T1CON
CCPR1L
CCPR1H
CCP1CON
TMR3L
TMR3H
T3CON
ADCON0
Legend:
Name
Special Event Trigger will:
RB3/CCP1/P1A pin
Reset Timer1 or Timer3, but does not set Timer1 or Timer3 interrupt flag bit
and set bit GO/DONE (ADCON0<2>), which starts an A/D conversion.
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
PORTB Data Direction Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
GIE/GIEH PEIE/GIEL
VCFG1
RD16
P1M1
RD16
Bit 7
—
—
—
Output Enable
TRISB<3>
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
COMPARE MODE OPERATION BLOCK DIAGRAM
T1RUN
VCFG0
P1M0
ADIF
ADIE
ADIP
Bit 6
—
Q
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
T3CKPS1 T3CKPS0
TMR0IE
DC1B1
R
S
RCIF
RCIE
RCIP
Bit 5
—
Special Event Trigger
CCP1CON<3:0>
Mode Select
Output
Logic
INT0IE
DC1B0
CHS2
TXIE
TXIP
Bit 4
TXIF
Set Flag bit CCP1IF
CCP1M3
T3CCP1
CHS1
RBIE
Bit 3
Match
—
—
—
CCP1M2
T3SYNC
TMR0IF
CCP1IF
CCP1IE
CCP1IP
CHS0
Bit 2
TMR1H
GO/DONE
TMR1CS TMR1ON 0000 0000 uuuu uuuu
CCP1M1
TMR3CS TMR3ON 0-00 0000 u-uu uuuu
TMR2IE
TMR2IP
TMR2IF
INT0IF
T3CCP1
Bit 1
TMR1L
CCPR1H CCPR1L
CCP1M0 0000 0000 0000 0000
TMR1IF -000 -000 -000 -000
TMR1IE -000 -000 -000 -000
TMR1IP -111 -111 -111 -111
ADON
Comparator
RBIF
Bit 0
© 2007 Microchip Technology Inc.
0
1
0000 000x 0000 000u
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
00-0 0000 00-0 0000
POR, BOR
Value on
TMR3H
TMR3L
Value on
all other
Resets
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