PIC18F1320-H/P Microchip Technology, PIC18F1320-H/P Datasheet - Page 124

• Manufacturer Part Number: PIC18F1320-H/P
• Description: IC MCU 8BIT 8KB FLASH 18PDIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1320-H/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

current in half-bridge power devices. The value of bits,
PIC18F1220/1320
15.5.4
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output
signal is output on the RB3/CCP1/P1A pin, while the
complementary PWM output signal is output on the
RB2/P1B/INT2 pin (Figure 15-6). This mode can be
used for half-bridge applications, as shown in
Figure 15-7, or for full-bridge applications, where four
power switches are being modulated with two PWM
signals.
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through
PDC6:PDC0 (PWM1CON<6:0>), sets the number of
instruction cycles before the output is driven active. If the
value is greater than the duty cycle, the corresponding
output remains inactive during the entire cycle. See
Section 15.5.6 “Programmable Dead-Band Delay”
for more details of the dead-band delay operations.
FIGURE 15-7:
DS39605F-page 122
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
HALF-BRIDGE MODE
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
PIC18F1220/1320
P1A
P1B
PIC18F1220/1320
P1A
P1B
FET
Driver
FET
Driver
FET
Driver
FET
Driver
The TRISB<3> and TRISB<2> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 15-6:
P1A
P1B
Note 1: At this time, the TMR2 register is equal to the
td = Dead-Band Delay
Load
V+
V-
(1)
PR2 register.
td
Duty Cycle
Period
Load
td
HALF-BRIDGE PWM
OUTPUT (ACTIVE-HIGH)
© 2007 Microchip Technology Inc.
FET
Driver
FET
Driver
(1)
+
V
-
+
V
-
Period
(1)