PIC18F4680-H/P Microchip Technology, PIC18F4680-H/P Datasheet - Page 232
PIC18F4680-H/P
Manufacturer Part Number
PIC18F4680-H/P
Description
IC MCU 8BIT 64KB FLASH 44PDIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F4585-IPT.pdf
(482 pages)
Specifications of PIC18F4680-H/P
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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PIC18F2585/2680/4585/4680
REGISTER 18-3:
DS39625C-page 230
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
BAUDCON: BAUD RATE CONTROL REGISTER
bit 7
ABDOVF: Auto-Baud Acquisition Rollover Status bit
1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode
0 = No BRG rollover has occurred
RCIDL: Receive Operation Idle Status bit
1 = Receive operation is Idle
0 = Receive operation is active
Unimplemented: Read as ‘0’
SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
Unused in this mode.
Synchronous mode:
1 = Idle state for clock (CK) is a high level
0 = Idle state for clock (CK) is a low level
BRG16: 16-bit Baud Rate Register Enable bit
1 = 16-bit Baud Rate Generator – SPBRGH and SPBRG
0 = 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored
Unimplemented: Read as ‘0’
WUE: Wake-up Enable bit
Asynchronous mode:
1 = EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit
0 = RX pin not monitored or rising edge detected
Synchronous mode:
Unused in this mode.
ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Enable baud rate measurement on the next character. Requires reception of a Sync field
0 = Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode.
Legend:
R = Readable bit
-n = Value at POR
ABDOVF
R/W-0
(must be cleared in software)
cleared in hardware on following rising edge
(55h); cleared in hardware upon completion
RCIDL
R-1
U-0
Preliminary
—
W = Writable bit
‘1’ = Bit is set
R/W-0
SCKP
BRG16
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
© 2007 Microchip Technology Inc.
x = Bit is unknown
R/W-0
WUE
ABDEN
R/W-0
bit 0
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