AM186CC-25KI\W C AMD (ADVANCED MICRO DEVICES), AM186CC-25KI\W C Datasheet - Page 28

• Manufacturer Part Number: AM186CC-25KI\W C
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM186CC-25KI\W C

• Lead Free Status / Rohs Status: Not Compliant

ARCHITECTURAL OVERVIEW
The architectural goal of the Am186CC microcontroller
is to provide comprehensive communications features
on a processor r unning the widely known x86
instr uction set. The Am186CC microcontroller
combines four HDLC channels, a USB peripheral
controller, and general communications peripherals
with the Am186 microcontroller. This highly integrated
Detailed Description
n Universal Serial Bus (USB) peripheral controller
n Four independent High-level Data Link Control
28
works with a wide variety of USB devices
– Implements high-speed 12-Mbit/s device function
– Allows an unlimited number of device descriptors
– Supports a total of six endpoints: one control
– Two data endpoints have 16-byte FIFOs; two
– Fully integrated differential driver directly
– Specialized hardware supports adaptive
– General-purpose DMA and SmartDMA™
(HDLC) channels support a wide range of
external interfaces
– External interface connection for HDLCs can be
Am186
CPU
endpoint; one interrupt endpoint; four data
endpoints that can be either bulk or isochronous,
IN or OUT
data endpoints have 64-byte FIFOs
supports the USB interface (D+, D–)
isochronous data streams
channels supported
PCM Highway, GCI, or raw DCE
to RAM/ROM
Glueless
Interface
Memory Peripherals
Selects
Chip
(14)
Controller
DRAM
PIOs
(48)
Am186™CC Communications Controller Data Sheet
Figure 1. Am186CC Controller Block Diagram
Watchdog
System Peripherals
Timer
Timers
(3)
General-
Purpose
DMA (4)
Controller
Sources)
Interrupt
(17 Ext.
microcontroller provides system cost and performance
advantages for a wide range of communications
applications. Figure 1 is a block diagram of the
Am186CC microcontroller, followed by sections
providing an overview of the features of the Am186CC
microcontroller.
– Data rate of up to 10 Mbit/s
– Receive and transmit FIFOs
– Support for HDLC, Synchronous Data Link
– Two dedicated buffer descriptor ring SmartDMA
– One independent time-slot assigner per HDLC
– Clear to Send/Ready to Receive (CTS/RTR)
– Collision detection for multidrop applications
– Transparency mode
– Address comparison on receive
– Flag or mark idle operation
SmartDMA
UART
Control (SDLC), Line Access Procedure
Balanced (LAP-B), Line Access Procedure D
(LAP-D), Point-to-Point Protocol (PPP), and
v.120 (support of v.110 in transparent mode)
channels per HDLC
hardware handshaking and auto-enable
operation
Channels
(8)
Serial Communications Peripherals
High-Speed
UART with
Autobaud
HDLC
HDLC
HDLC
HDLC
TSA
TSA
TSA
TSA
USB
Muxing
Interface (SSI)
Synchronous
GCI (IOM-2)
Raw DCE
Interface
Highway
Serial
Physical
PCM