AT89C51RD2-RDTIM Atmel, AT89C51RD2-RDTIM Datasheet - Page 24

• Manufacturer Part Number: AT89C51RD2-RDTIM
• Description: MCU 8-Bit AT89 80C51 CISC 64KB Flash 3.3V/5V 64-Pin VQFP Tray
• Manufacturer: Atmel

9.1
24
Registers
AT89C51RD2/ED2
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM)
internal data memory. The stack may not be located in the XRAM.
The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses are
extended from 6 to 30 clock periods. This is useful to access external slow peripherals.
Table 9-1.
AUXR - Auxiliary Register (8Eh)
• With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in
• With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard
Number
part of the available XRAM as explained in Table 9-1. This can be useful if external
peripherals are mapped at addresses already used by the internal XRAM.
combination with any of the registers R0, R1 of the selected bank or DPTR. An access to
XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM =
0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H
rather than external memory. An access to external data memory locations higher than the
accessible size of the XRAM will be performed with the MOVX DPTR instructions in the same
way as in the standard 80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7
as write and read timing signals. Accesses to XRAM above 0FFH can only be done by the
use of DPTR.
80C51.MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0 and any
output port pins can be used to output higher order address bits. This is to provide the
external paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs
the high-order eight address bits (the contents of DPH) while Port0 multiplexes the low-order
eight address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read
or write signals on P3.6 (WR) and P3.7 (RD).
DPU
Bit
7
7
6
5
4
3
2
Mnemonic
AUXR Register
XRS2
XRS1
XRS0
DPU
Bit
M0
6
-
-
Description
Disable Weak Pull-up
Cleared by software to activate the permanent weak pull-up (default)
Set by software to disable the weak pull-up (reduce power consumption)
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Pulse length
Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock periods
0
0
0
0
1
(default).
Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods.
XRAM Size
XRS2 XRS1 XRS0 XRAM size
M0
5
0
0
1
1
0
0
1
0
1
0
XRS2
4
256 bytes
512 bytes
768 bytes(default)
1024 bytes
1792 bytes
XRS1
3
XRS0
2
EXTRAM
1
4235J–8051–01/08
AO
0