PIC10F206-I/OT Microchip Technology, PIC10F206-I/OT Datasheet - Page 56
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PIC10F206-I/OT
Manufacturer Part Number
PIC10F206-I/OT
Description
MCU 8-Bit PIC10 PIC RISC 768Byte Flash 2.5V/3.3V/5V 6-Pin SOT-23 Bag
Manufacturer
Microchip Technology
Datasheet
1.PIC10F200T-IOT.pdf
(96 pages)
Specifications of PIC10F206-I/OT
Package
6SOT-23
Device Core
PIC
Family Name
PIC10
Maximum Speed
4 MHz
Ram Size
24 Byte
Program Memory Size
768 Byte
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
3
Operating Temperature
-40 to 85 °C
Number Of Timers
1
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC10F206-I/OT
Manufacturer:
MICROC
Quantity:
28 000
Part Number:
PIC10F206-I/OT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC10F200/202/204/206
BTFSS
Syntax:
Operands:
Operation:
Status Affected: None
Description:
CALL
Syntax:
Operands:
Operation:
Status Affected: None
Description:
CLRF
Syntax:
Operands:
Operation:
Status Affected: Z
Description:
DS41239D-page 54
Bit Test f, Skip if Set
[ label ] BTFSS f,b
0 ≤ f ≤ 31
0 ≤ b < 7
skip if (f<b>) = 1
If bit ‘b’ in register ‘f’ is ‘1’, then the
next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruc-
tion fetched during the current
instruction execution, is discarded
and a NOP is executed instead,
making this a two-cycle instruction.
Subroutine Call
[ label ] CALL k
0 ≤ k ≤ 255
(PC) + 1→ Top-of-Stack;
k → PC<7:0>;
(STATUS<6:5>) → PC<10:9>;
0 → PC<8>
Subroutine call. First, return
address (PC + 1) is PUSHed onto
the stack. The eight-bit immediate
address is loaded into PC
bits <7:0>. The upper bits
PC<10:9> are loaded from
STATUS<6:5>, PC<8> is cleared.
CALL is a two-cycle instruction.
Clear f
[ label ] CLRF
0 ≤ f ≤ 31
00h → (f);
1 → Z
The contents of register ‘f’ are
cleared and the Z bit is set.
f
CLRW
Syntax:
Operands:
Operation:
Status Affected: Z
Description:
CLRWDT
Syntax:
Operands:
Operation:
Status Affected: TO, PD
Description:
COMF
Syntax:
Operands:
Operation:
Status Affected: Z
Description:
Clear W
[ label ] CLRW
None
00h → (W);
1 → Z
The W register is cleared. Zero bit
(Z) is set.
Clear Watchdog Timer
[ label ] CLRWDT
None
00h → WDT;
0 → WDT prescaler (if assigned);
1 → TO;
1 → PD
The CLRWDT instruction resets the
WDT. It also resets the prescaler, if
the prescaler is assigned to the
WDT and not Timer0. Status bits
TO and PD are set.
Complement f
[ label ] COMF
0 ≤ f ≤ 31
d ∈ [0,1]
(f) → (dest)
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back in
register ‘f’.
© 2007 Microchip Technology Inc.
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