KMPC8548EVTAUJC Freescale Semiconductor, KMPC8548EVTAUJC Datasheet - Page 35

• Manufacturer Part Number: KMPC8548EVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548EVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Figure 15
8.2.5
When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant
eTSEC interface. In single-clock TBI mode, when TBICON[CLKSEL] = 1, a 125-MHz TBI receive clock
is supplied on the TSECn_RX_CLK pin (no receive clock is used on TSECn_TX_CLK in this mode,
whereas for the dual-clock mode this is the PMA1 receive clock). The 125-MHz transmit clock is applied
on the TSEC_GTX_CLK125 pin in all TBI modes.
A summary of the single-clock TBI mode AC specifications for receive appears in
Freescale Semiconductor
RX_CLK clock period
RX_CLK duty cycle
RX_CLK peak-to-peak jitter
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
RCG[9:0] setup time to RX_CLK rising edge
RCG[9:0] hold time to RX_CLK rising edge
shows the TBI receive AC timing diagram.
TBI Single-Clock Mode AC Specifications
TSECn_RX_CLK1
TSECn_RX_CLK0
Parameter/Condition
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
RCG[9:0]
Table 32. TBI single-clock Mode Receive AC Timing Specification
Figure 15. TBI Receive AC Timing Diagram
t
t
SKTRX
TRXH
t
TRDVKH
t
TRX
t
TRXH
Valid Data
t
TRRH/TRRX
t
t
Symbol
TRRDXKH
TRRDVKH
t
t
t
t
TRRX
TRRR
TRRF
TRRJ
t
TRXF
Valid Data
t
TRDXKH
Min
7.5
2.0
1.0
40
—
—
—
t
TRXR
t
TRDVKH
Enhanced Three-Speed Ethernet (eTSEC)
t
TRDXKH
Typ
8.0
50
—
—
—
—
—
Table
Max
32.
250
8.5
1.0
1.0
60
—
—
Unit
ns
ps
ns
ns
ns
ns
%
35