RC28F128P33BF60A Micron Technology Inc, RC28F128P33BF60A Datasheet - Page 52

• Manufacturer Part Number: RC28F128P33BF60A
• Manufacturer: Micron Technology Inc

Specifications of RC28F128P33BF60A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Figure 19: Asynchronous Page-Mode Read Timing
Note:
Figure 20: Synchronous Single-Word Array or Non-array Read Timing
Notes:
1.
2.
Datasheet
52
A[Max:4] [A]
DATA [D/Q]
WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by
CE# deassertion after the first word in the burst.
ADV# [V]
WAIT [T]
Address [A]
Data [D/Q]
OE# [G]
CE# [E]
ADV# [V]
WAIT [T]
OE# [G]
CLK [C]
CE# [E]
A[3:1]
.
R105
R105
R105
R105
R101
R301
R303
R104
R104
R101
R102
R6
R2
R3
R15
R4
0
R306
R106
R7
Q0
R2
R3
R10
R4
Valid Address
R108
1
Q1
R106
R307
R304
R10
2
R108
Q2
R305
R10
R312
R108
R9
7
R17
R8
Q 7
Order Number: 208034-04
R9
R10
R8
R13
P33-65nm
Jul 2011