LTC4271IUF#PBF Linear Technology, LTC4271IUF#PBF Datasheet - Page 22
![](/photos/40/80/408078/qfnep-24_sml.jpg)
LTC4271IUF#PBF
Manufacturer Part Number
LTC4271IUF#PBF
Description
Manufacturer
Linear Technology
Datasheet
1.LTC4271IUFPBF.pdf
(32 pages)
Specifications of LTC4271IUF#PBF
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Pin Count
24
Mounting
Surface Mount
Package Type
QFN EP
Case Length
4mm
Screening Level
Industrial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
LTC4270/LTC4271
APPLICATIONS INFORMATION
the Port Status register will always report the results of the
last class pulse, so an invalid Class 4–Class 2 combination
would report a second class pulse was run in the High
Power Status register (which implies that the first cycle
found class 4), and Class 2 in the Port Status register.
POWER CONTROL
The primary function of the LTC4270/LTC4271 is to con-
trol the delivery of power to the PSE port. It does this by
controlling the gate drive voltage of an external power
MOSFET while monitoring the current via an external sense
resistor and the output voltage at the OUT pin. This circuitry
serves to couple the raw V
a controlled manner that satisfies the PDs power needs
while minimizing both power dissipation in the MOSFET
and disturbances on the V
Inrush Control
Once the command has been given to turn on a port, the
LTC4270/LTC4271 ramps up the GATE pin of that port’s
external MOSFET in a controlled manner. Under normal
power-up circumstances, the MOSFET gate will rise until
the port current reaches the inrush current limit level
(typically 425mA), at which point the GATE pin will be
servoed to maintain the specified I
this inrush period, a timer (t
charging is complete, the port current will fall and the GATE
pin will be allowed to continue rising to fully enhance the
MOSFET and minimize its on-resistance. The final V
nominally 13V. The inrush period is maintained until the
t
level is still exceeded, the port will be turned back off and
a t
Current Limit
Each LTC4270/LTC4271 port includes two current limiting
thresholds (I
timer (t
depends on several factors: the class of the PD, the volt-
22
START
START
timer expires. At this time if the inrush current limit
CUT
fault reported.
and t
CUT
LIM
and I
). Setting the I
LIM
EE
), each with a corresponding
EE
backplane.
input supply to the port in
START
CUT
INRUSH
) runs. When output
and I
current. During
LIM
thresholds
GS
is
age of the main supply (V
Type 2), the sense resistor (0.5Ω or 0.25Ω), the SOA of
the MOSFET, and whether or not the system is required
to enforce class current levels.
Per the IEEE specification, the LTC4270/LTC4271 will al-
low the port current to exceed I
time before removing power from the port, whereas it will
actively control the MOSFET gate drive to keep the port
current below I
limit the current when only the I
but does start the t
the I
t
counts up. If the t
port is turned off and the port t
the current limit circuitry to tolerate intermittent overload
signals with duty cycles below about 6%; longer duty cycle
overloads will turn the port off.
The I
tively limiting port current. The t
when the t
to a shorter value than t
MOSFET protection and turn off a port before MOSFET
damage can occur. The t
threshold is exceeded. When the t
(typical) the port is turned off and the port t
set. When the t
are tracked by the t
I
I
port to tolerate minor faults without current limiting.
Per the IEEE specification, the LTC4270/LTC4271 will au-
tomatically set I
during inrush at port turn-on, and then switch to the
programmed I
maintain IEEE compliance, I
for all Type 1 PDs, and 850mA if a Type 2 PD is detected.
I
CUT
LIM
CUT
LIM
is automatically reset to 425mA when a port turns off.
and I
CUT
is typically set to a lower value than I
timer counts back down, but at 1/16 the rate that it
LIM
current limiting circuit is always enabled and ac-
current threshold before its timer expires, the
CUT
LIM
events.
Enable bit is set. This allows t
LIM
LIM
LIM
LIM
setting once inrush has completed. To
. The port does not take any action to
CUT
CUT
CUT
Enable bit is disabled t
to 425mA (shown in bold in Table 5)
timer, which counts up during both
timer reaches 60ms (typical) the
timer. If the current drops below
CUT
LIM
EE
LIM
), the type of PSE (Type 1 or
to provide more aggressive
timer starts when the I
CUT
CUT
CUT
should be kept at 425mA
LIM
LIM
fault is set. This allows
threshold is exceeded,
for a limited period of
timer is enabled only
timer reaches 12ms
LIM
LIM
LIM
to allow the
LIM
behaviors
to be set
fault is
42701f
LIM