IS43DR16160A-25EBLI ISSI, Integrated Silicon Solution Inc, IS43DR16160A-25EBLI Datasheet - Page 35

• Manufacturer Part Number: IS43DR16160A-25EBLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS43DR16160A-25EBLI

• Lead Free Status / Rohs Status: Compliant

IS43/46DR83200A, IS43/46DR16160A
DDR2 SDRAM Mode Register Set (MRS)
Notes:
1. For DDR2-400/533, WR (write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min. WR in clock
2. Speed bin determined. Refer to Key Timing Parameter table.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
05/24/2011
Address
cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer (WR[cycles] = RU{ tWR[ns] / tCK[ns] }, where RU
stands for round up). For DDR2-667/800, WR min is determined by tCK(avg) max and WR max is determined by tCK(avg) min. WR[cycles] =
RU{ tWR[ns] / tCK(avg)[ns] }, where RU stands for round up. The mode register must be programmed to this value. This is also used with tRP
to determine tDAL.
Field
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Latency
Register
Length
CAS
Burst
Mode
WR
DLL
TM
BT
PD
0
0
A11
A12
A8
A6
A3
0
1
0
0
0
0
1
1
1
1
0
1
0
0
0
0
1
1
1
1
0
1
A10
Active power down exit time
A5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Slow exit(use tXARDS)
Fast exit (use tXARD)
Burst Type
DLL Reset
Sequential
Interleave
Yes
No
A9
A4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
WR(cycles)
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2
3
4
5
6
5
6
3
4
2
2
2
2
*1
A7
A2
0
1
0
0
-
-
-
5
5
5
5
-
tCK (ns) for speed option
A1
1
1
3.75
3.75
3.75
-
-
-
5
-
Reserved
Normal
Mode
A0
0
1
3.75
3
3
-
-
-
5
-
BL
4
8
3.75
2
2.5
-
-
-
5
-
3
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