DS2152L+ Maxim Integrated Products, DS2152L+ Datasheet
DS2152L+
Specifications of DS2152L+
Related parts for DS2152L+
DS2152L+ Summary of contents
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... Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. Enhanced T1 Single-Chip Transceiver PIN CONFIGURATION TOP VIEW R Formats ORDERING INFORMATION PART DS2152L DS2152L+ DS2152LN DS2152LN+ + Denotes lead-free/RoHS-compliant package DS2152 DS2152 1 LQFP ...
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DETAILED DESCRIPTION....................................................................................................6 1.1 I ................................................................................................................................ 6 NTRODUCTION 1.1.1 New Features......................................................................................................................................... 6 1 UNCTIONAL ESCRIPTION 1.3 R ’ N .............................................................................................................................. 7 EADER S OTE 2 PIN DESCRIPTION................................................................................................................9 2 RANSMIT IDE IGITAL 2 ...
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Receive an HDLC Message or a BOC................................................................................................. 59 12.1.4 Transmit an HDLC Message................................................................................................................ 59 12.1.5 Transmit a BOC ................................................................................................................................... 59 12.1.6 HDLC/BOC Register Description ......................................................................................................... 60 12.2 L FDL S EGACY UPPORT 12.2.1 Receive Section ................................................................................................................................... 67 12.2.2 Transmit ...
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Figure 1-1. DS2152 Enhanced T1 Single-Chip Transceiver ...................................................................... 8 Figure 15-1. External Analog Connections............................................................................................... 78 Figure 15-2. Jitter Tolerance .................................................................................................................... 78 Figure 15-3. Transmit Waveform Template .............................................................................................. 79 Figure 15-4. Jitter Attenuation .................................................................................................................. 79 Figure 16-1. Receive Side D4 Timing....................................................................................................... ...
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Table 2-1. Register Map ........................................................................................................................... 15 Table 4-1. Output Pin Test Modes............................................................................................................ 22 Table 5-1. Receive T1 Level Indication .................................................................................................... 34 Table 5-2. Alarm Criteria .......................................................................................................................... 36 Table 6-1. Line Code Violation Counting Arrangements .......................................................................... 40 Table 6-2. Path Code ...
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DETAILED DESCRIPTION The DS2152 T1 enhanced single-chip transceiver (SCT) contains all the necessary functions for connection to T1 lines, whether they be DS-1 long haul or DSX-1 short haul. The clock recovery circuitry automatically adjusts to T1 lines from ...
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Functional Description The analog AMI/B8ZS waveform off the T1 line is transformer-coupled into the RRING and RTIP pins of the DS2152. The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux ...
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Figure 1-1. DS2152 Enhanced T1 Single-Chip Transceiver ...
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PIN DESCRIPTION PIN NAME 1 RCHBLK 7–10, 15, 23, N.C. 26, 27, 28, 36, 54 8MCLK 6 RCL 11 BTS 12 LIUC 13 8XCLK 14 TEST 16 RTIP 17 RRING 18 RVDD 19, 20, ...
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PIN NAME 57 D1/AD1 58 D2/AD2 59 D3/AD3 62 D4/AD4 63 D5/AD5 64 D6/AD6 65 D7/AD7 66–72 A0–A6 73 A7/ALE 74 RD(DS WR(R/W) 78 RLINK 79 RLKCLK 82 RCLK 85 RDATA 86 RPOSI 87 RNEGI 88 RCLKI ...
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Transmit Side Digital Pins PIN NAME Transmit Clock. A 1.544MHz primary clock. Used to clock data through the transmit 46 TCLK side formatter. Transmit Serial Data. Transmit NRZ serial data. Sampled on the falling edge of 47 TSER TCLK ...
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PIN NAME transmitted out onto the T1 line. Can be internally connected to TPOSO by tying the LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications. Transmit Negative Data Input. Sampled on the falling edge of ...
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PIN NAME Receive Loss of Sync/Loss of Transmit Clock. A dual function output that is controlled by the CCR3.5 control bit. This pin can be programmed to either toggle high 99 RLOS/LOTC when the synchronizer is searching for the frame ...
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Line Interface Pins PIN NAME Master Clock Input. A 1.544MHz (±50ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both clock/data recovery and for jitter 21 MCLK attenuation. A quartz crystal ...
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Table 2-1. Register Map ADDRESS R/W 00 R/W FDL Control 01 R/W FDL Status 02 R/W FDL Interrupt Mask 03 R/W Receive Performance Report Message 04 R/W Receive Bit Oriented Code 05 R Receive FDL FIFO 06 R/W Transmit Performance ...
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ADDRESS R/W 33 R/W Transmit Channel Blocking 2 34 R/W Transmit Channel Blocking 3 35 R/W Transmit Control 1 36 R/W Transmit Control 2 37 R/W Common Control 1 38 R/W Common Control 2 39 R/W Transmit Transparency 1 3A ...
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ADDRESS R Receive Signaling Receive Signaling Receive Signaling Receive Signaling Receive Signaling Receive Signaling 12 6C R/W Receive Channel Blocking 1 6D R/W ...
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PARALLEL PORT The DS2152 is controlled via either a nonmultiplexed (MUX = multiplexed (MUX = 1) bus by an external microcontroller or microprocessor. The DS2152 can operate with either Intel or Motorola bus timing configurations. If ...
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RCR1: RECEIVE CONTROL REGISTER 1 (Address = 2B Hex) (MSB) LCVCRF ARC SYMBOL POSITION LCVCRF RCR1.7 ARC RCR1.6 OOF1 RCR1.5 OOF2 RCR1.4 SYNCC RCR1.3 SYNCT RCR1.2 SYNCE RCR1.1 RESYNC RCR1.0 OOF1 OOF2 SYNCC NAME AND DESCRIPTION Line Code Violation Count ...
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RCR2: RECEIVE CONTROL REGISTER 2 (Address = 2C Hex) (MSB) RCS RZBTSI RSDW SYMBOL POSITION RCS RCR2.7 RZBTSI RCR2.6 RSDW RCR2.5 RSM RCR2.4 RSIO RCR2.3 RD4YM RCR2.2 FSBE RCR2.1 MOSCRF RCR2.0 RSM RSIO RD4YM NAME AND DESCRIPTION Receive Code Select. ...
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TCR1: TRANSMIT CONTROL REGISTER 1 (Address = 35 Hex) (MSB) LOTCMC TFPT SYMBOL POSITION LOTCMC TCR1.7 TFPT TCR1.6 TCPT TCR1.5 TSSE TCR1.4 GB7S TCR1.3 TFDLS TCR1.2 TBL TCR1.1 TYEL TCR1.0 Note: For a description of how the bits in TCR1 ...
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TCR2: TRANSMIT CONTROL REGISTER 2 (Address = 36 Hex) (MSB) TEST1 TEST0 TZBTSI SYMBOL POSITION TEST1 TCR2.7 TEST0 TCR2.6 TZBTSI TCR2.5 TSDW TCR2.4 TSM TCR2.3 TSIO TCR2.2 TD4YM TCR2.1 TB7ZS TCR2.0 Table 4-1. Output Pin Test Modes TEST 1 TEST ...
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CCR1: COMMON CONTROL REGISTER 1 (Address = 37 Hex) (MSB) TESE ODF RSAO SYMBOL POSITION TESE CCR1.7 ODF CCR1.6 RSAO CCR1.5 TSCLKM CCR1.4 RSCLKM CCR1.3 RESE CCR1.2 PLB CCR1.1 FLB CCR1.0 TSCLKM RSCLKM NAME AND DESCRIPTION Transmit Elastic Store Enable. ...
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Payload Loopback When CCR1.1 is set to 1, the DS2152 is forced into Payload Loopback (PLB). Normally, this loopback is only enabled when ESF framing is being performed but can be enabled also in D4 framing applications ...
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CCR2: COMMON CONTROL REGISTER 2 (Address = 38 Hex) (MSB) TFM TB8ZS TSLC96 SYMBOL POSITION TFM CCR2.7 TB8ZS CCR2.6 TSLC96 CCR2.5 TFDL CCR2.4 RFM CCR2.3 RB8ZS CCR2.2 RSLC96 CCR2.1 RFDL CCR2.0 TFDL RFM RB8ZS NAME AND DESCRIPTION Transmit Frame Mode ...
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CCR3: COMMON CONTROL REGISTER 3 (Address = 30 Hex) (MSB) ESMDM ESR RLOSF SYMBOL POSITION ESMDM CCR3.7 ESR CCR3.6 RLOSF CCR3.5 RSMS CCR3.4 PDE CCR3.3 ECUS CCR3.2 TLOOP CCR3.1 — CCR3.0 RSMS PDE NAME AND DESCRIPTION Elastic Store Minimum Delay ...
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CCR4: COMMON CONTROL REGISTER 4 (Address = 11 Hex) (MSB) RSRE RPCSI RFSA1 SYMBOL POSITION RSRE CCR4.7 RPCSI CCR4.6 RFSA1 CCR4.5 RFE CCR4.4 RFF CCR4.3 THSE CCR4.2 TPCSI CCR4.1 TIRFS CCR4.0 RFE RFF NAME AND DESCRIPTION Receive Side Signaling Reinsertion ...
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CCR5: COMMON CONTROL REGISTER 5 (Address = 19 Hex) (MSB) TJC LLB SYMBOL POSITION TJC CCR5.7 LLB CCR5.6 LIAIS CCR5.5 TCM4 CCR5.4 TCM3 CCR5.3 TCM2 CCR5.2 TCM1 CCR5.1 TCM0 CCR5.0 LIAIS TCM4 TCM3 NAME AND DESCRIPTION Transmit Japanese CRC6 Enable. ...
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CCR6: COMMON CONTROL REGISTER 6 (Address = 1E Hex) (MSB) RJC — SYMBOL POSITION RJC CCR6.7 — CCR6.6 — CCR6.5 RCM4 CCR6.4 RCM3 CCR6.3 RCM2 CCR6.2 RCM1 CCR6.1 RCM0 CCR6.0 CCR7: COMMON CONTROL REGISTER 7 (Address = 0A Hex) (MSB) ...
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Power-Up Sequence On power-up, after the supplies are stable, the DS2152 should be configured for operation by writing to all the internal registers (this includes setting the Test Registers to 00 hex) since the contents of the internal registers ...
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STATUS AND INFORMATION REGISTERS There is a set of nine registers that contain information on the current real-time status of the DS2152: Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Registers (RIR1/RIR2/RIR3), and a ...
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RIR1: RECEIVE INFORMATION REGISTER 1 (Address = 22 Hex) (MSB) COFA 8ZD SYMBOL POSITION COFA RIR1.7 8ZD RIR1.6 16ZD RIR1.5 RESF RIR1.4 RESE RIR1.3 SEFE RIR1.2 B8ZS RIR1.1 FBE RIR1.0 16ZD RESF RESE NAME AND DESCRIPTION Change of Frame Alignment. ...
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RIR2: RECEIVE INFORMATION REGISTER 2 (Address = 31 Hex) (MSB) RLOSC LRCLC SYMBOL POSITION RLOSC RIR2.7 LRCLC RIR2.6 TESF RIR2.5 TESE RIR2.4 TSLIP RIR2.3 RBLC RIR2.2 RPDV RIR2.1 TPDV RIR2.0 TESF TESE TSLIP NAME AND DESCRIPTION Receive Loss of Sync ...
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RIR3: RECEIVE INFORMATION REGISTER 3 (Address = 10 Hex) (MSB) RL1 RL0 SYMBOL POSITION RL1 RIR3.7 RL0 RIR3.6 JALT RIR3.5 LORC RIR3.4 FRCL RIR3.3 — RIR3.2, RIR3.1, RIR3.0 Table 5-1. Receive T1 Level Indication TYPICAL LEVEL RL1 RL0 0 0 ...
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SR1: STATUS REGISTER 1 (Address = 20 Hex) (MSB) LUP LDN SYMBOL POSITION LUP SR1.7 LDN SR1.6 LOTC SR1.5 RSLIP SR1.4 RBL SR1.3 RYEL SR1.2 LRCL SR1.1 RLOS SR1.0 LOTC RSLIP RBL NAME AND DESCRIPTION Loop Up Code Detected. Set ...
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Table 5-2. Alarm Criteria ALARM Blue Alarm (AIS) (See note 1 below) Yellow Alarm (RAI bit 2 mode(RCR2 F-bit mode (RCR2.2=1; this mode is also referred to as the "Japanese Yellow Alarm" ...
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SR2: STATUS REGISTER 2 (Address = 21 Hex) (MSB) RMF TMF SYMBOL POSITION RMF SR2.7 TMF SR2.6 SEC SR2.5 RFDL SR2.4 TFDL SR2.3 RMTCH SR2.2 RAF SR2.1 RSC SR2.0 SEC RFDL TFDL NAME AND DESCRIPTION Receive Multiframe. Set on receive ...
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IMR1: INTERRUPT MASK REGISTER 1 (Address = 7F Hex) (MSB) LUP LDN SYMBOL POSITION LUP IMR1.7 LDN IMR1.6 LOTC IMR1.5 SLIP IMR1.4 RBL IMR1.3 RYEL IMR1.2 LRCL IMR1.1 RLOS IMR1.0 LOTC SLIP RBL NAME AND DESCRIPTION Loop Up Code Detected. ...
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IMR2: INTERRUPT MASK REGISTER 2 (Address = 6F Hex) (MSB) RMF TMF SYMBOL POSITION RMF IMR2.7 TMF IMR2.6 SEC IMR2.5 RFDL IMR2.4 TFDL IMR2.3 RMTCH IMR2.2 RAF IMR2.1 RSC IMR2.0 SEC RFDL TFDL NAME AND DESCRIPTION Receive Multiframe ...
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ERROR COUNT REGISTERS There are a set of three counters in the DS2152 that record bipolar violations, excessive 0s, errors in the CRC6 codewords, framing bit errors, and number of multiframes that the device is out of receive synchronization. ...
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Path Code Violation Count Register (PCVCR) When the receive side of the DS2152 is set to operate in the ESF framing mode (CCR2.3 = 1), PCVCR will automatically be set as a 12-bit counter that will record errors in ...
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MOSCR1: MULTIFRAMES OUT OF SYNC COUNT REGISTER 1 (Address = 25 Hex) MOSCR2: MULTIFRAMES OUT OF SYNC COUNT REGISTER 2 (Address = 27 Hex) (MSB) MOS/FB MOS/FB MOS/ MOS/FB MOS/FB MOS/ SYMBOL POSITION MOS/FB11 MOSCR1.7 MOS/FB0 ...
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DS0 MONITORING FUNCTION The DS2152 can monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel ...
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CCR5: COMMON CONTROL REGISTER 5 (Address = 19 Hex) (Repeated here from Section 4 for convenience.) (MSB) TJC LLB SYMBOL POSITION TJC CCR5.7 LLB CCR5.6 LIAIS CCR5.5 TCM4 CCR5.4 TCM3 CCR5.3 TCM2 CCR5.2 TCM1 CCR5.1 TCM0 CCR5.0 LIAIS TCM4 TCM3 ...
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TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address = 1A Hex) (MSB SYMBOL POSITION B1 TDS0M.7 B2 TDS0M.6 B3 TDS0M.5 B4 TDS0M.4 B5 TDS0M.3 B6 TDS0M.2 B7 TDS0M.1 B8 TDS0M.0 CCR6: COMMON CONTROL REGISTER 6 (Address = 1E Hex) (Repeated ...
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RDS0M: RECEIVE DS0 MONITOR REGISTER (Address = 1F Hex) (MSB SYMBOL POSITION B1 RDS0M.7 B2 RDS0M.6 B3 RDS0M.5 B4 RDS0M.4 B5 RDS0M.3 B6 RDS0M.2 B7 RDS0M.1 B8 RDS0M NAME AND DESCRIPTION Receive DS0 Channel Bit ...
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SIGNALING OPERATION The DS2152 contains provisions for both processor based (i.e., software based) signaling bit access and for hardware-based access. Both the processor-based access and the hardware-based access can be used simultaneously if necessary. The processor based signaling is ...
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A change in the signaling bits from one multiframe to the next will cause the RSC status bit (SR2. set. The user can enable the INT pin to toggle low upon detection of a change in signaling by ...
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Hardware-Based Signaling 8.2.1 Receive Side In the receive side of the hardware based signaling, there are two operating modes for the signaling buffer: signaling extraction and signaling reinsertion. Signaling extraction involves pulling the signaling bits from the receive data ...
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PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK The DS2152 can replace data on a channel-by-channel basis in both the transmit and receive directions. The transmit direction is from the backplane to the T1 line and is covered in Section 9.1. ...
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TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address = 3F Hex) (MSB) TIDR7 TIDR6 TIDR5 SYMBOL POSITION TIDR7 TIDR.7 TIDR0 TIDR.0 9.1.2 Per-Channel Code Insertion The second method involves using the Transmit Channel Control Registers (TCC1/2/3) to determine which of the 24 ...
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Receive Side Code Generation In the receive direction there are also two methods by which channel data to the backplane can be overwritten with data generated by the DS2152. The first method, which is covered in Section 9.2.1, was ...
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RCC1/RCC2/RCC3: RECEIVE CHANNEL CONTROL REGISTER (Address = Hex) (MSB) CH8 CH7 CH6 CH16 CH15 CH14 CH24 CH23 CH22 SYMBOL POSITION CH24 RCC3.7 CH1 RCC1.0 CH5 CH4 CH3 CH13 CH12 CH11 CH21 CH20 CH19 NAME AND DESCRIPTION Receive ...
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CLOCK BLOCKING REGISTERS The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins, respectively. The RCHBLK and TCHCLK pins are user-programmable outputs that can be forced either high or low ...
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ELASTIC STORES OPERATION The DS2152 contains dual two-frame (386 bits) elastic stores: one for the receive direction and one for the transmit direction. These elastic stores have two main purposes. First, they can be used to rate convert the ...
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Minimum Delay Synchronous RSYSCLK/TSYSCLK Mode In applications where the DS2152 is connected to backplanes that are frequency-locked to the recovered T1 clock (i.e., the RCLK output), the full two-frame depth of the on-board elastic stores is really not needed. ...
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FDL/FS EXTRACTION AND INSERTION The DS2152 can extract/insert data from/into the Facility Data Link (FDL) in the ESF framing mode and from/into Fs-bit position in the D4 framing mode. Because SLC-96 uses the Fs-bit position, this capability can also ...
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Like the other status registers in the DS2152, the user will always precede a read of any of the four registers with a write. The byte written to the register will inform the DS2152 which of the latched bits the ...
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Receive an HDLC Message or a BOC 1) Enable RBOC and RPS interrupts. 2) Wait for interrupt to occur RBOC = 1, then follow steps 5 and RPS = 1, then follow steps 7 ...
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HDLC/BOC Register Description FDLC: FDL CONTROL REGISTER (Address = 00 Hex) (MSB) RBR RHR SYMBOL POSITION RBR FDLC.7 RHR FDLC.6 TFS FDLC.5 THR FDLC.4 TABT FDLC.3 TEOM FDLC.2 TZSD FDLC.1 TCRCD FDLC.0 TFS THR TABT NAME AND DESCRIPTION Receive ...
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FDLS: FDL STATUS REGISTER (Address = 01 Hex) (MSB) RBOC RPE SYMBOL POSITION RBOC FDLS.7 RPE FDLS.6 RPS FDLS.5 RHALF FDLS.4 RNE FDLS.3 THALF FDLS.2 TNF FDLS.1 TMEND FDLS.0 Note: The RBOC, RPE, RPS, and TMEND bits are latched and ...
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FIMR: FDL INTERRUPT MASK REGISTER (Address = 02 Hex) (MSB) RBOC RPE SYMBOL POSITION RBOC FIMR.7 RPE FIMR.6 RPS FIMR.5 RHALF FIMR.4 RNE FIMR.3 THALF FIMR.2 TNF FIMR.1 TMEND FIMR.0 RPS RHALF RNE NAME AND DESCRIPTION Receive BOC Detector Change ...
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RPRM: RECEIVE RPM REGISTER (Address = 03 Hex) (MSB) RABT RCRCE ROVR SYMBOL POSITION RABT RPRM.7 RCRCE RPRM.6 ROVR RPRM.5 RVM RPRM.4 REMPTY RPRM.3 POK RPRM.2 CBYTE RPRM.1 OBYTE RPRM.0 Note: The RABT, RCRCE, ROVR, and RVM bits are latched ...
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RBOC: RECEIVE BOC REGISTER (Address = 04 Hex) (MSB) LBD BD SYMBOL POSITION LBD RBOC.7 BD RBOC.6 BOC5 RBOC.5 BOC4 RBOC.4 BOC3 RBOC.3 BOC2 RBOC.2 BOC1 RBOC.1 BOC0 RBOC.0 Note 1: The LBD bit is latched and will be cleared ...
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TPRM: TRANSMIT PRM REGISTER (Address = 06 Hex) (MSB) — — SYMBOL POSITION — TPRM.7 to TPRM.3 TEMPTY TPRM.2 TFULL TPRM.1 UDR TPRM.0 Note: The UDR bit is latched and will be cleared when read. TBOC: TRANSMIT BOC REGISTER (Address ...
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TFFR: TRANSMIT FDL FIFO REGISTER (Address = 08 Hex) (MSB) FDL7 FDL6 SYMBOL POSITION FDL7 TFFR.7 FDL6 TFFR.6 FDL5 TFFR.5 FDL4 TFFR.4 FDL3 TFFR.3 FDL2 TFFR.2 FDL1 TFFR.1 FDL0 TFFR.0 FDL5 FDL4 FDL3 NAME AND DESCRIPTION FDL Data Bit 7. ...
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Legacy FDL Support In order to provide backward compatibility to the older DS2151 device, the DS2152 maintains the circuitry that existed in the previous generation of T1 single-chip transceivers. This section covers the circuitry and operation of this legacy ...
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RFDLM1: RECEIVE FDL MATCH REGISTER 1 (Address = 29 Hex) RFDLM2: RECEIVE FDL MATCH REGISTER 2 (Address = 2A Hex) (MSB) RFDL7 RFDL6 RFDL5 SYMBOL POSITION RFDL7 RFDL.7 RFDL0 RFDL.0 When the byte in the Receive FDL Register matches either ...
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D4/SLC-96 OPERATION In the D4 framing mode, the DS2152 uses the TFDL register to insert the Fs framing pattern. To allow the device to properly insert the Fs framing pattern, the TFDL register at address 7Eh must be programmed ...
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PROGRAMMABLE IN-BAND CODE GENERATION AND DETECTION The DS2152 can generate and detect a repeating bit pattern that is from bits in length. To transmit a pattern, the user will load the pattern to be sent into ...
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Table 13-1. Transmit Code Length LENGTH TC1 TC0 SELECTED (BITS Table 13-2. Receive Code Length RUP2/ RUP1/ RUP0/ RDN2 RDN1 RDN0 ...
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RUPCD: RECEIVE UP CODE DEFINITION REGISTER (Address = 14 Hex) (MSB SYMBOL POSITION C7 RUPCD.7 C6 RUPCD.6 C5 RUPCD.5 C4 RUPCD.4 C3 RUPCD.3 C2 RUPCD.2 C1 RUPCD.1 C0 RUPCD NAME AND DESCRIPTION Receive Up Code ...
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RDNCD: RECEIVE DOWN CODE DEFINITION REGISTER (Address = 15 Hex) (MSB SYMBOL POSITION C7 RDNCD.7 C6 RDNCD.6 C5 RDNCD.5 C4 RDNCD.4 C3 RDNCD.3 C2 RDNCD.2 C1 RDNCD.1 C0 RDNCD NAME AND DESCRIPTION Receive Down Code ...
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TRANSMIT TRANSPARENCY Each of the 24 T1 channels in the transmit direction of the DS2152 can be either forced to be transparent or, in other words, can be forced to stop Bit 7 Stuffing and/or Robbed Signaling from overwriting ...
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LINE INTERFACE FUNCTION The line interface function in the DS2152 contains three sections: the receiver, which handles clock and data recovery; the transmitter, which waveshapes and drives the T1 line; and the jitter attenuator. Each of these three sections ...
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Receive Clock and Data Recovery The DS2152 contains a digital clock recovery system. See The DS2152 couples to the receive T1 twisted pair via a 1:1 transformer. See details. The 1.544MHz clock attached at the MCLK pin is internally ...
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Table 15-2. Transformer Specifications SPECIFICATION Turns Ratio Primary Inductance Leakage Inductance Intertwining Capacitance DC Resistance 15.3 Jitter Attenuator The DS2152 contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits via the ...
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Figure 15-1. External Analog Connections NOTE 1: RESISTOR VALUES ARE ±1%. NOTE 2: THE R RESISTORS ARE USED TO PROTECT THE DEVICE FROM OVERVOLTAGE. T NOTE 3: SEE THE SEPARATE APPLICATION NOTE FOR DETAILS ON HOW TO CONSTRUCT A PROTECTED ...
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Figure 15-3. Transmit Waveform Template Figure 15-4. Jitter Attenuation ...
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TIMING DIAGRAMS Figure 16-1. Receive Side D4 Timing NOTE 1: RSYNC IN THE FRAME MODE (RCR2 AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (RCR2.5 = 0). NOTE 2: RSYNC IN THE FRAME MODE (RCR2 AND ...
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Figure 16-3. Receive Side Boundary Timing (with Elastic Store Disabled) NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24. NOTE 2: SHOWN IS RLINK/RLCLK IN THE ESF FRAMING MODE. Figure 16-4. Receive Side 1.544MHz Boundary Timing (with Elastic Store Enabled) ...
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Figure 16-5. Receive Side 2.048MHz Boundary Timing (with Elastic Store Enabled) NOTE 1: RSER DATA IN CHANNELS 13, 17, 21, 25, AND 29 ARE FORCED TO 1. NOTE 2: RSYNC IS IN THE OUTPUT MODE (RCR2.3 = ...
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Figure 16-7. Transmit Side Timing NOTE 1: TSYNC IN THE FRAME MODE (TCR2 AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (TCR2.4 = 0). NOTE 2: TSYNC IN THE FRAME MODE (TCR2.3=0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (TCR2.4 ...
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Figure 16-9. Transmit Side 1.544MHz Boundary Timing (with Elastic Store Enabled) NOTE 1: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24 (IF THE TPCSI BIT IS SET, THEN THE SIGNALING DATA AT TSIG WILL BE IGNORED DURING CHANNEL 24). Figure 16-10. ...
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Figure 16-11. Transmit Data Flow NOTE 1: TCLK SHOULD BE TIED TO RCLK AND TSYNC SHOULD BE TIED TO RFSYNC FOR DATA TO BE PROPERLY SOURCED FROM RSER ...
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DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………..-1.0V to +7.0V Operating Temperature Range Commercial……………………………………………………………………………0°C to +70°C Industrial…………………………………………………………………………….-40°C to +85°C Storage Temperature……………………………………………………………………….-55°C to +125°C Soldering Temperature……………………………………………See IPC/JEDEC STD-020 Specification This is a stress rating only ...
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AC CHARACTERISTICS Table 18-1. AC Characteristics—Multiplexed Parallel Port (MUX = ± 0°C to +70°C for DS2152L (See Figure 18-1, Figure 18-2, and PARAMETER Cycle Time Pulse Width, DS ...
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Figure 18-2. Intel Bus Write AC Timing (BTS = 0/MUX = 1) Figure 18-3. Motorola Bus AC Timing (BTS = 1/MUX = ...
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Table 18-2. AC Characteristics—Receive Side = 5V ± 0°C to +70°C for DS2152L (See Figure 18-4, Figure 18-5, and PARAMETER RCLKO Period RCLKO Pulse Width RCLKO Pulse Width RCLKI Period RCLKI Pulse ...
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Figure 18-4. Receive Side AC Timing NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR2.3 = 0). NOTE 2: SHOWN IS RLINK/RLCLK IN THE ESF FRAMING MODE. NOTE 3: NO RELATIONSHIP BETWEEN RCHCLK AND RCHBLK AND THE OTHER SIGNALS IS ...
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Figure 18-5. Receive System Side AC Timing NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR2.3 = 0). NOTE 2: RSYNC IS IN THE INPUT MODE (RCR2.3 = 1). Figure 18-6. Receive Line Interface AC Timing ...
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Table 18-3. AC Characteristics—Transmit Side = 5V ± 0°C to +70°C for DS2152L (See Figure 18-7, Figure 18-8, and PARAMETER TCLK Period TCLK Pulse Width TCLKI Period TCLKI Pulse Width TSYSCLK Period ...
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Figure 18-7. Transmit Side AC Timing NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR2.2 = 1). NOTE 2: TSYNC IS IN THE INPUT MODE (TCR2.2 = 0). NOTE 3: TSER IS SAMPLED ON THE FALLING EDGE OF TCLK WHEN ...
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Figure 18-8. Transmit System Side AC Timing NOTE 1: TSER IS ONLY SAMPLED ON THE FALLING EDGE OF TSYSCLK WHEN THE TRANSMIT SIDE ELASTIC STORE IS ENABLED. NOTE 2: TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TSYSCLK WHEN THE TRANSMIT SIDE ...
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Table 18-4. AC Characteristics—Nonmultiplexed Parallel Port (MUX = ± 0°C to +70°C for DS2152L (See Figure 18-10, Figure 18-11, PARAMETER Setup Time for Valid to Active ...
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Figure 18-11. Intel Bus Write AC Timing (BTS=0/MUX=0) Figure 18-12. Motorola Bus Read AC Timing (BTS = 1/MUX = 0) Figure 18-13. Motorola Bus Write AC Timing (BTS = 1/MUX = ...
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