DS21554L+ Maxim Integrated Products, DS21554L+ Datasheet - Page 56
DS21554L+
Manufacturer Part Number
DS21554L+
Description
IC TXRX E1 1-CHIP 5V 100-LQFP
Manufacturer
Maxim Integrated Products
Datasheet
1.DS2154LNA2.pdf
(124 pages)
Specifications of DS21554L+
Function
Single-Chip Transceiver
Interface
E1, HDLC, J1, T1
Number Of Circuits
1
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Includes
Remote and AIS Alarm Detector / Generator
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
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9. SIGNALING OPERATION
The DS21354/DS21554 contain provisions for both processor-based (i.e., software-based) signaling bit
access and for hardware-based access. Both the processor-based access and the hardware-based access
can be used simultaneously if necessary. The processor-based signaling is covered in Section
hardware based signaling is covered in Section 9.2. When referring to signaling, the voice-channel
numbering scheme is used.
9.1.
The Channel-Associated Signaling (CAS) bits embedded in the E1 stream can be extracted from the
receive stream and inserted into the transmit stream by the framer. Each of the 30 voice channels has four
signaling bits (A/B/C/D) associated with it. The numbers in parentheses () are the voice channel
associated with a particular signaling bit. The voice channel numbers have been assigned as described in
the ITU documents. Please note that this is different than the channel numbering scheme (1 to 32) that is
used in the rest of the data sheet.
For example, voice channel 1 is associated with time slot 1 (Channel 2) and voice channel 30 is
associated with time slot 31 (Channel 32). There is a set of 16 registers for the receive side (RS1 to RS16)
and 16 registers on the transmit side (TS1 to TS16). The signaling registers are detailed below.
RS1 TO RS16: RECEIVE SIGNALING REGISTERS (Address = 30 to 3F Hex)
SYMBOL
(MSB)
A(10)
A(11)
A(12)
A(13)
A(14)
A(15)
A(1)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
D(30)
0
A(1)
X
Y
Processor-Based Signaling
B(10)
B(11)
B(12)
B(13)
B(14)
B(15)
B(1)
B(2)
B(3)
B(4)
B(5)
B(6)
B(7)
B(8)
B(9)
0
POSITION
RS1.0/1/3
RS2.7 1.
RS16.0
RS1.2
C(10)
C(11)
C(12)
C(13)
C(14)
C(15)
C(1)
C(2)
C(3)
C(4)
C(5)
C(6)
B(7)
C(8)
C(9)
0
Spare Bits
Remote Alarm Bit (integrated and reported in SR1.6)
Signaling Bit A for Channel 1
Signaling Bit D for Channel 30
D(10)
D(11)
D(12)
D(13)
D(14)
D(15)
D(1)
D(2)
D(3)
D(4)
D(5)
D(6)
D(8)
D(9)
B(7)
0
A(16)
A(17)
A(18)
A(19)
A(20)
A(21)
A(23)
A(24)
A(25)
A(26)
A(27)
A(28)
A(29)
A(30)
B(22)
X
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NAME AND DESCRIPTION
B(16)
B(17)
B(18)
B(19)
B(20)
B(21)
B(22)
B(23)
B(24)
B(25)
B(26)
B(27)
B(28)
B(29)
B(30)
Y
C(16)
C(17)
C(18)
C(19)
C(20)
C(21)
B(22)
C(23)
C(24)
C(25)
C(26)
C(27)
C(28)
C(29)
C(30)
X
(LSB)
D(16)
D(17)
D(18)
D(19)
D(20)
D(21)
D(23)
D(24)
D(25)
D(26)
D(27)
D(28)
D(29)
D(30)
B(22)
X
RS1 (30)
RS2 (31)
RS3 (32)
RS3 (33)
RS5 (34)
RS6 (35)
RS7 (36)
RS8 (37)
RS9 (38)
RS10 (39)
RS11 (3A)
RS12 (3B)
RS13 (3C)
RS14 (3D)
RS15 (3E)
RS16 (3F)
9.1
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