SI3220-GQ Silicon Laboratories Inc, SI3220-GQ Datasheet - Page 72
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SI3220-GQ
Manufacturer Part Number
SI3220-GQ
Description
IC SLIC/CODEC DUAL-CH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Specifications of SI3220-GQ
Function
Subscriber Line Interface Concept (SLIC), CODEC
Interface
GCI, PCM, SPI
Number Of Circuits
2
Voltage - Supply
3.3V, 5V
Current - Supply
65mA
Power (watts)
941mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
*
Includes
Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI3220-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
SI3220-GQ
Manufacturer:
SILICONLABS/芯科
Quantity:
20 000
Company:
Part Number:
SI3220-GQR
Manufacturer:
SILICON
Quantity:
15 000
Si3220/Si3225
Figures 45 and 46 illustrate WRITE and READ
operations to register addresses via a 16-bit SPI
controller. These operations require a 4-byte transfer
arranged as two 16-bit words. The absence of CS going
high after the eighth bit of data indicates to the SPI state
machine that eight more SCLK pulses follow to
complete the operation. For a WRITE operation, the last
eight bits are ignored. For a read operation, the 8-bit
data value repeats so that the data is captured during
the last half of a data transfer if required by the
controller.
During register accesses, the CONTROL, ADDRESS,
and DATA are captured in the SPI module. At the
completion of the ADDRESS byte of a READ access,
the contents of the addressed register move into the
data register of the SPI data register. At the completion
of the DATA byte of a WRITE access, the data is
transferred from the SPI to the addressed register.
72
CS
SCLK
SDI
SDO
CS
SCLK
SDI
SDO
CS
SCLK
SDI
SDO
CONTROL
Figure 44. Register Read Operation via an 8-Bit SPI Port
Figure 45. Register Write Operation via a 16-Bit SPI Port
Figure 46. Register Read Operation via a 16-Bit SPI Port
CONTROL
CONTROL
ADDRESS
ADDRESS
Rev. 1.0
ADDRESS
Figures 47–50 illustrate the various cycles for accessing
RAM addresses. RAM addresses are 16-bit entities;
therefore, the accesses always require four bytes.
During RAM address accesses, the CONTROL,
ADDRESS, and DATA are captured in the SPI module.
At the completion of the ADDRESS byte of a READ
access, the contents of the channel-based data buffer
move into the data register in the SPI for shifting out
during the DATA portion of the SPI transfer. This is the
data loaded into the data buffer in response to the
previous RAM address read request. Therefore, there is
a one-deep pipeline nature to RAM address READ
operations. At the completion of the DATA portion of the
READ cycle, the ADDRESS is transferred to the
channel-based address buffer register, and a RAM
address is logged for that channel. The RAMSTAT bit in
each channel is polled to monitor the status of RAM
address accesses that are serviced twice per sample
period at dedicated windows in the DSP algorithm.
Data [7:0]
X X X X X X X X
Data [7:0]
Same byte repeated twice.
X X X X X X X X
X X X X X X X X
Data [7:0]
X X X X X X X X
Data [7:0]
Hi - Z