SI3220-KQ Silicon Laboratories Inc, SI3220-KQ Datasheet
SI3220-KQ
Specifications of SI3220-KQ
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SI3220-KQ Summary of contents
Page 1
... On-chip subscriber loop and audio testing allows remote diagnostics and fault detection with no external test equipment or relays. The Si3220 and Si3225 operate from a single 3 supply and interface to standard PCM/SPI or GCI bus digital interfaces. The Si3200 linefeed interface IC performs all high voltage functions and operates from a 3 ...
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... Si3220/Si3225 Dual ProSLIC Selection Guide Part Description Number Si3200-KS Linefeed interface Si3200-BS Linefeed interface Si3220-KQ Dual ProSLIC Si3220-BQ Dual ProSLIC Si3225-KQ Dual ProSLIC Si3225-BQ Dual ProSLIC 2 On-Chip External Pulse Metering Ringing Ringing Support " " " " " " Preliminary Rev. 0.91 ...
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... PCM Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 General Circuit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 System Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8-Bit Control Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 16-Bit RAM Address Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Pin Descriptions: Si3220/ 101 Pin Descriptions: Si3200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Dual ProSLIC Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Package Outline: 64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Contact Information ...
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... Si3220/Si3225 Electrical Specifications Table 1. Absolute Maximum Ratings and Thermal Information Parameter Supply Voltage, Si3200 and Si3220/ Si3225 High Battery Supply Voltage, Si3200 Low Battery Supply Voltage, Si3200 TIP or RING Voltage, Si3205 TIP, RING Current, Si3200 STIPAC, STIPDC, SRINGAC, SRINGDC Current, Si3220/Si3225 ...
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... Table 2. Recommended Operating Conditions Parameter Ambient Temperature Ambient Temperature Supply Voltage, Si3220/Si3225 Supply Voltage, Si3200 High Battery Supply Voltage, Si3200 Low Battery Supply Voltage, Si3200 *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 Table 3 ...
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... Si3220/Si3225 Table 3. 3.3 V Power Supply Characteristics ( – °C for K-Grade, – °C for B-Grade) DD DD1 DD4 A Parameter Symbol V Supply Current I BAT VBAT (Si3200) Power Consumption P SLEEP P OPEN P STBY P STBY P ACTIVE P ACTIVE P OHT P OHT P RING *Note: All specifications are for a single channel based on measurements with both channels in the same operating state. ...
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... K-Grade, – °C for B-Grade) DD DD1 DD4 A Parameter Symbol V –V Supply I –I DD1 DD4 VDD1 Current (Si3220/Si3225) V Supply Current I DD VDD (Si3200) V Supply Current I BAT VBAT (Si3200) *Note: All specifications are for a single channel based on measurements with both channels in the same operating state. * ...
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... Si3220/Si3225 Table Power Supply Characteristics ( – °C for K-Grade, – °C for B-Grade) DD DD1 DD4 A Parameter Symbol Power Consumption P SLEEP P OPEN P STBY P STBY P ACTIVE P ACTIVE P OHT P OHT P RING *Note: All specifications are for a single channel based on measurements with both channels in the same operating state. ...
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... Hz to 3.4 kHz Step size around 0 dB 200 Hz to 3.4 kHz – Assumes ideal line impedance matching. RING = 600 Ω 600 Ω synthesized using RS register coefficients Preliminary Rev. 0.91 Si3220/Si3225 Min Typ Max Unit 2.5 — — V Figure 6 — — ...
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... Si3220/Si3225 Table 5. AC Characteristics (Continued –V = 3. °C for K-Grade, – °C for B-Grade) DD DD1 DD4 A Parameter 5 Transhybrid Balance 6 Idle Channel Noise PSRR from V –V DD1 DD4 Longitudinal to Metallic/PCM Balance (forward or reverse) Metallic/PCM to Longitudinal Balance 7 Longitudinal Impedance 7 Longitudinal Current per Pin Notes: 1 ...
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... V RING I <I ; RING to ground RING LIM TIP to ground THR THR Si3220, ac detection, VRING = 70 Vpk, no offset 80mA TH Si3220, dc detection offset Si3225, dc Detection, = 1500 Ω offset, R loop Open circuit 100 V BATH = 0 Ω, 5 REN load, R LOOP V = 100 V BATH THD 100 Hz Accuracy of ON/OFF times ↑ ...
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... Si3220/Si3225 Table 6. Linefeed Characteristics (Continued –V = 3. DD1 DD4 A Parameter Symbol Loop Current Sense Accuracy Power Alarm Threshold Accuracy *Note: Ringing amplitude is set for 93 V peak using the RINGAMP RAM address and measured at TIP-RING using no series protection resistance. Table 7. Monitor ADC Characteristics ...
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... DTX, SDO, INT, SDITHRU – BATSELa/b, RRDa/b, GPOa/b, TRD1a/b, TRD2a/ – –V = 3.13 V DD1 DD4 IO < –V = 3.13 V DD1 DD4 IO < Preliminary Rev. 0.91 Si3220/Si3225 Min Typ Max 0.7 x — 5. — — 0 – 0.6 — — — — 0.4 — — ...
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... Si3220/Si3225 Table 11. Switching Characteristics—General Inputs ( –V = 3. °C for K-Grade, – °C for B-Grade DD1 DD4 A Parameter Rise Time, RESET 2 RESET Pulse Width, GCI Mode RESET Pulse Width, SPI Daisy Chain Mode Notes: 1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are V ...
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... Preliminary Rev. 0.91 Si3220/Si3225 pF Units Typ Max — 3906 ns 256 — kHz 512 — kHz 768 — kHz 1.024 — MHz 1.536 — MHz 1.544 — ...
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... Si3220/Si3225 Table 13. Switching Characteristics—PCM Highway Interface (Continued –V = 3. °C for K-Grade, – °C for B-Grade DD1 DD4 A Parameter Delay Time, PCLK Rise to DTX 3 Tristate Setup Time, FSYNC to PCLK Fall Hold Time, FSYNC to PCLK Fall Setup Time, DRX to PCLK Fall ...
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... Frame 0, Bit 0 Preliminary Rev. 0.91 Si3220/Si3225 Min Typ Max Units — 488 — ns — 244 — ns µ s — 125 — — — ±120 ns — — — — — — — — — — — — ...
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... Si3220/Si3225 PCLK t su1 FSYNC Frame 0, DRX Bit 0 DTX Figure 4. GCI Highway Interface Timing Diagram (4.096 MHz PCLK Mode) Acceptable Region Figure 5. Transmit and Receive Path SNDR su2 Frame 0, Bit 0 Preliminary Rev. 0. ...
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... Figure 7. Transmit Path Frequency Response Acceptable Region Fundamental Input Power (dBm0) TX Attenuation Distortion Frequency (Hz) TX Pass−Band Detail Frequency (Hz) Preliminary Rev. 0.91 Si3220/Si3225 19 ...
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... Si3220/Si3225 5 0 −5 −10 −15 −20 −25 −30 −35 −40 −45 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1 −1.2 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000 Figure 8 ...
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... RX Group Delay Distortion 1100 1000 900 800 700 600 500 400 300 200 Typical Response 100 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400 Frequency (Hz) Figure 10. Receive Group Delay Distortion Preliminary Rev. 0.91 Si3220/Si3225 21 ...
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Transmit Path Decimation + A/D Filter Codec Loopback DLM3 Interpolation D buf m From Billing Tone DAC Receive Path Figure 11. AC Signal Path Block Diagram for a Single Channel Decimation + THPF ...
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... TIPb TIPb_ext TIPb 5 4 RINGb 3 RINGb_ext RINGb 2 1 RJ-11 SMD TP4 C33 C31 0.1u 0.1u 100V 100V VBAT VBATH VBLO Figure 12. Si3220 Application Circuit Using Dual Battery Supply VDD U2 Si3200 1 16 TIP ITIPP ITIPN 3 14 RING THERM 4 13 VBAT IRINGP 5 12 ...
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J1 TP1 Tip A K1 Protection 6 2 TIPa_ext TIPa RINGa_ext RINGa VDD 7 1 C30 RJ-11 SMD RR Da 0.1u 10 100V DPDT Ring A VBHI TP2 C3 C4 10n ...
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... Bill of Materials Table 15. Si3220 + Si3200 External Component Values Component C1, C2, C11, C12 100 nF, 100 V, X7R, ±20% C3, C4, C13, C14 10 nF, 100 V, X7R, ±20% 1 µF, 6.3 V, X7R, ±20% C5, C6, C15, C16 0.1 µF, 100 V, Y5V C30–C33 0.1 µ Y5V C20–C25 R1, R2, R11, R12 402 kΩ ...
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... The Si3220 and Si3225 can also be configured to support a 4-wire general circuit hybrid, and test interface (GCI). The Si3220 and Si3225 are available in a 64-lead TQFP and the Si3200 is available in a 16-lead SOIC. Dual ProSLIC Architecture The Dual ProSLIC chipset is comprised of a low-voltage ...
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... R and DC OV RING; Capacitor C the TIP and RING leads to be measured. The Si3220 and Si3225 both use the Si3200 to drive TIP and RING and isolate the high-voltage line from the low-voltage CMOS devices. The Si3220 and Si3225 measure voltage at various nodes to monitor the linefeed current ...
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... Figure 15. Simplified Dual ProSLIC Linefeed Architecture for TIP and RING Leads (diagram illustrates either TIP or RING lead of a single channel) 28 Low Frequency Diagnostic Filters Monitor A/D A/D DSP D/A SLIC DAC Σ SLIC Control Loop Si3200 Battery Current Select Mirror Control Preliminary Rev. 0.91 Si3220/ Si3225 SLIC Control V Sense BAT R BAT ...
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... Si3200. Forward Active (LF[2:0] = 001). Linefeed is active, but audio paths are powered down until an off-hook condition is detected. The Si3220 and Si3225 automatically enter a low power state to reduce power consumption during on-hook standby periods. Forward On-Hook Transmission (LF[2:0] = 010). ...
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... V VOVRING[14: 63.3 V VOCTRACK[15: 63.3 V During the on-hook state, the Si3220/Si3225 is in the constant voltage operating area and typically presents a 640 Ω output impedance (Figure 16). The Si3220 and - TIP ) is Si3225 include a special modified linefeed scheme LIM called Modfeed impedance based on the linefeed voltage level in order to ensure the ability to source extended loop lengths ...
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... VOCTRACK LIM by an amount programmed into the VOCLTH RAM location. Exceeding this threshold causes the Si3220/ Si3225 to increase its “target” V Loop Closure Threshold programmed into the VOCDELTA RAM location to provide additional overhead for driving the higher Constant impedance loop ...
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... Si3220/Si3225 Only one calibration should be necessary if the system remains powered up. To optimize performance recommended that the user perform the following steps when running the CAL routines: 1. Set CALR1 = 0x3F and CALR2 = 0x3E. This enables all calibration routines except the AC longitudinal balance (CALCMBAL) routine ...
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... Thermometer-Based Si3200 Power Monitor The Si3200 includes an on-chip analog thermal sensing diode that provides realtime die temperature data to the Si3220/3225 provided the THERMSEL bit is set to 1. The analog thermometer has a built in temperature threshold which, when exceeded, turns off the Si3200 and asserts the STAT bit of the THERM register. The internal temperature threshold is set to approximately 140 ° ...
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... Si3220/Si3225 comparator output and remains high until the user clears it. Each transistor power alarm bit is also maskable by setting the PQ1E–PQ6E bits in the IRQEN3 register. Si3200 Power Calculation When using the Si3200 also possible to control thermal temperature rise by calculating the total power dissipated within the IC ...
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... The Dual ProSLIC chipset is designed with the ability to source long loop lengths in excess of 18 kft, but can also accommodate short loop configurations. For example, the Si3220 can operate from one of two battery supplies depending on the operating state. When in the on-hook state, the on-hook loop feed is generated from the ringing battery supply, generally – ...
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... Si3220/Si3225 provided in Table 21. The primary input to the system is the loop current sense value from the voltage/current/ power monitoring circuitry and reported in the ILOOP RAM address. The LCS value is processed in the input signal processor (ISP) provided the LFS bits in the Linefeed register indicate the device Active or On-Hook Transmission state ...
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... LONGDBI. If the debounce interval is satisfied, the LONGHI bit is set to indicate that a valid loop closure has occurred. Digital + LPF Debounce – LONGLPF LONGDBI Ground Key Threshold LONGHITH LONGLOTH Preliminary Rev. 0.91 Si3220/Si3225 2 3.097 µ A 396.4 µ A 3.097 µ A 396.4 µ 101. 4000h N/A N 40.96s 1.25 ms 1.25 ms programming ...
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... BATL low enough to allow proper operation from the lower supply. When using the Si3220, this mode should always be enabled to allow seamless switching between the ringing and off-hook states. The same switching scheme is used with the Si3225 to reduce power by switching to a lower off-hook battery when sourcing a short loop ...
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... SVBAT 806 kΩ V BATL V BATH Figure 22. External Battery Switching Using the Si3220/Si3225 equation below and is entered into the BATLPF RAM location. BATLPF = [(2 π 4096)/800 the high battery Where f = the desired cutoff frequency of the filter The programmable range of the filter is from 0 (blocks all signals) to 4000h (unfiltered) ...
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... Figure 22. The Si3220’s BATSEL pin is used to switch between the VBATH (typically –48 V) and VBATL (typically –24 V) rails using the switch internal to the Si3200. The Si3220’ ...
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... RINGTALO/ RINGTA[15:0] RINGTAHI RINGTILO/ RINGTI[15:0] RINGTIHI LINEFEED LF[2:0] VOC VOC[15:0] RINGOF RINGOF[15:0] RINGFRHI/ RINGFRHI[14:3]/ RINGFRLO RINGFRLO[14:3] RINGAMP RINGAMP[15:0] Preliminary Rev. 0.91 Si3220/Si3225 ( ) 0.09Ω per foot for 26AWG wire = R 320Ω = OUT 7000Ω ----------------- - R = LOAD #REN Programmable Resolution Range (LSB Size) ...
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... Si3220/Si3225 Table 25. Register and RAM Locations Used for Ringing Generation (Continued) Parameter Ringing Initial Phase Sinusoidal Trapezoid External Ringing Ringing Relay Driver Enable (Si3225 only) Ringing Overhead Voltage Internal Sinusoidal Ringing A sinusoidal ringing waveform is generated by the on- chip digital tone generator. The tone generator used to generate ringing tones is a two-pole resonator with a programmable frequency and amplitude ...
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... TIP-RING V OFF T = 1/freq t RISE Figure 26. Trapezoidal Ringing Waveform Ringing DC Offset Voltage A dc offset voltage can be added to the Si3220’s ac ringing waveform by programming the RINGOF RAM location to the appropriate setting. The value of RINGOF is calculated as follows: RINGOF External Unbalanced Ringing The Si3225 supports ...
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... Therefore ring trip detection scheme is required when sourcing longer loop lengths. The Si3220 can implement either an ac- or dc-based ring trip detection scheme, depending on the application. The Si3225 allows external dc ring trip detection when using a battery-backed external ringing generator by monitoring the ringing feed path through two sensing inputs on each channel ...
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... Full Wave ILOOP Signal Rectifier Processor Figure 27. Ring Trip Detect Processing Circuitry RTACTH AC Ring Trip Threshold _ Debounce Filter_AC Digital + LPF RTACDB RTPER Digital + LPF _ DC Ring Trip Threshold RTDCTH Preliminary Rev. 0.91 Si3220/Si3225 RTP Interrupt RTRIPS Logic RTRIPE Debounce Filter_DC RTDCDB 45 ...
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... Hz. The Si3220 also can add a dc offset component to the ringing signal and detect a ring trip event by monitoring the dc loop current flowing once the terminal equipment transitions to the off-hook state ...
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... Table 28 provides recommended values for R for typical relay characteristics and V DRV supplies. The output impedance (R driver pins is a constant 63 Ω while sourcing less than the maximum rated 28 mA out of the pin. Preliminary Rev. 0.91 Si3220/Si3225 V/5 V Relay (polarized or non-polarized) RRDa/b TRD1a/b ...
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... Si3220/Si3225 Si3220/ Si3225 Figure 29. Driving Relays with V The maximum allowable R value can be calculated with the following equation: DRV MaxR DRV Table 28. Recommended R ProSLIC V Relay V DD 3.3 V ±5% 3.3 V ± ± ±5% 3.3 V ± ±5% 3.3 V ± ±10% 3.3 V ± ±10% 3.3 V ± ± ...
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IRINGXSCAL D ZERDELAY COUNTER0 COUNTER1 RINGEN RRD On LF LFSDELAY LFS Ringing Figure 30. Timing Characteristics for Ringing Relay Control ...
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... Si3220/Si3225 V V 510 Ω OFF RING _ + 806 kΩ 806 kΩ Si3225 Figure 31. Si3225 External Ring Trip Circuitry Ringing Relay Activation During Zero Crossings The Si3225 is for applications that use a centralized ringing generator and a per-channel ringing relay to connect the ringing signal to the TIP/RING pair. The ...
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... Figure 32 illustrates the wink function. Programmable Range Register/RAM See table 15 LF[2:0] Read only POLREV 1 = Ramp VOCZERO 0 = Return to previous Disabled PREN 1 = Enabled V/1.25 ms RAMP V/1.25 ms Preliminary Rev. 0.91 Si3220/Si3225 Polarity reversal is then Register/RAM Bits Mnemonic LINEFEED POLREV POLREV POLREV POLREV 51 ...
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... Si3220/Si3225 V (V) TIP/RING Set VOCZERO bit to 1 Figure 32. Wink Function with Programmable Ramp Rate Two-Wire Impedance Synthesis Two-wire impedance synthesis is performed on-chip to optimally match the output impedance of the Dual ProSLIC to the impedance of the subscriber loop to minimize the receive path signal reflected back onto the transmit path ...
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... Control and status register bits are placed in the figure to indicate their association with the tone generator architecture. The register set for tone generation is summarized in Table 31 on page 55. Preliminary Rev. 0.91 Si3220/Si3225 53 ...
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... Si3220/Si3225 8 kHz Clock OSCnEN Zero 16-Bit Cross OSCnTA Modulo Logic Expire Counter OSCnTI Expire OSCnTA INT OSCnTAEN Logic OSCnTI INT OSCnTIEN Logic *Tone Generator 1 Only n = "1" or "2" for Tone Generator 1 and 2, respectively Oscillator Frequency and Amplitude Each of the two tone generators contains a two-pole ...
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... OSC2TI[15:0] OMODE, OCON ZEROEN2, ROUT2, ENSYNC2, OSC2TAEN, OSC2TIEN, OSC2EN IRQVEC1, IRQEN1 OS2TAS, OS2TIS, OS2TAE, OS2TIE Preliminary Rev. 0.91 Si3220/Si3225 Description/Range (LSB Size) Sets oscillator frequency Sets oscillator amplitude Sets initial phase (default = 8.19 s (125 µ 8.19 s (125 µs) Enables all Oscillator 1 param- ...
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... Si3220/Si3225 OSC1EN ... ... 0,1 , OSC1TA ENSYNC1 Tone Gen. 1 Signal Output Figure 36. Tone Generator Timing Diagram First Ring Burst Message Message Parameter 1 Type Length Message Header Parameter Type Figure 37. On-Hook Caller ID Transmission Sequence 56 ... ... 0,1 , OSC1TI 0,1 Channel Mark Seizure Packet Parameter 2 Message Body ...
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... Pulse Metering Generation The Si3220 offers an additional tone generator to generate tones above the audio frequency band. This oscillator generates billing tones which are typically 12 kHz or 16 kHz. The generator follows the same bit ...
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... Si3220/Si3225 coeff – 15 × PMAMPL ----------------------- - – coeff + where Full Scale V PK The pulse metering oscillator has a volume envelope (linear ramp) on the on/off transitions of the oscillator. The ramp is controlled by the value in the PMRAMP RAM address, and the sinusoidal generator output is multiplied by this volume before it is sent to the Pulse Metering DAC ...
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... Figure 38. Pulse Metering Generation Block Diagram DTMF Detection On-chip DTMF detection, also known as Touch Tone, is available in the Si3220 and Si3225 in-band signaling system that replaces the pulse- dial signaling standard. In DTMF, two tones generate a DTMF digit. One tone is chosen from the four possible row tones and one tone is chosen from the four possible column tones ...
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... Si3220/Si3225 Table 36. DTMF Hex Codes Digit Hex code 1 0x1 2 0x2 3 0x3 4 0x4 5 0x5 6 0x6 7 0x7 8 0x8 9 0x9 0 0xA * 0xB # 0xC A 0xD B 0xE C 0xF D 0x0 Modem Tone Detection The Dual ProSLIC devices are capable of detecting a 2100 Hz modem tone as described Recommendation V.8. The detection scheme can be implemented in both transmit and receive paths, and is enabled by programming the appropriate register bit ...
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... PLL_MULT register. However, the settling time depends on the PCLK frequency and it is approximately predicted by the following equation 64/F settle PCLK VCO DIV M PLL_MULT Preliminary Rev. 0.91 Si3220/Si3225 , BUF paths, although implemented 1.544 MHz, 2.048 MHz, ÷2 ÷2 28.672 MHz ...
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... Si3220/Si3225 Interrupt Logic The Dual ProSLIC devices are capable of generating interrupts for the following events: ! Loop current/ring ground detected. ! Ring trip detected. ! Ground Key detected. ! Power alarm. ! DTMF digit detected. ! Active timer 1 expired. ! Inactive timer 1 expired. ! Active timer 2 expired. ! Inactive timer 2 expired. ...
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... SPI transaction. (See Figure 42 broadcast to all devices connected to the chain is requested, the CID does not decrement. In this case, the same 8-bit or 16-bit data is pre- sented to all channels regardless of the CID values CID[0] CID[1] Table 37. SPI Control Interface Preliminary Rev. 0.91 Si3220/Si3225 CID[2] CID[3] 63 ...
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... Si3220/Si3225 Channel 0 CS SDO Channel 1 Channel 2 CS SDO Channel 3 Channel 14 CS SDO Channel 15 Figure 41. SPI Daisy-Chain Mode Preliminary Rev. 0.91 SDI0 SDI SDI1 Dual P roS LIC #1 SDITHRU SDI2 SDI SDI3 Dual P roS LIC #2 SDITHRU SDI4 SDI14 SDI SDI15 Dual P roS LIC #8 ...
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... BRDCST 0 SDI0 0 SDI1 (Internal) 0 SDI2 0 SDI3 (Internal) 0 SDI 14 0 SDI15 (Internal) 1 SDI0-15 Figure 42. Sample SPI Control Word to Address Channel 0 SPI Control Word REG/RAM Reserved CID[0] R Preliminary Rev. 0.91 Si3220/Si3225 CID[1] CID[2] CID[ ...
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... Si3220/Si3225 Figures 43 and 44 illustrate WRITE and READ operations to register addresses via an 8-bit SPI controller. These operations are performed as a 3-byte transfer asserted between each byte which is required for asserted before the first falling edge of SCLK after the DATA byte to indicate to the state machine that one byte should be transferred. The state of SDI is a “ ...
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... By keeping the address, data buffers, and RAMSTAT register on a per channel basis, RAM address accesses can be scheduled for both channels without interface. ADDRESS DATA [15:8] ADDRESS DATA [15:8] Preliminary Rev. 0.91 Si3220/Si3225 DATA [7:0] Hi DATA [7:0] 67 ...
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... Si3220/Si3225 CS SCLK SDI CONTROL SDO Figure 49. RAM Write Operation via a 16-Bit SPI Port CS SCLK SDI CONTROL SDO Figure 50. RAM Read Operation via a 16-Bit SPI Port 68 ADDRESS Data [15:8] ADDRESS Data [15:8] Preliminary Rev. 0.91 Data [7: Data [7:0] ...
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... PCLK cycles in a sample period the PCMTXHI, stops data transmission because PCMTXHI/PCMTXLO or PCMRXHI/PCMRXLO do not equal the PCLK count. Figures 51–53 illustrate the usage of the PCM highway interface to adapt to common PCM standards MSB LSB MSB LSB LSB LSB Preliminary Rev. 0.91 Si3220/Si3225 HI HI-Z 69 ...
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... Si3220/Si3225 PCM Companding The Dual ProSLIC devices support both µ-255 Law (µ- Law) and A-Law companding formats in addition to Linear Data mode. The data format is selected via the PCMF bits of the PCM Mode Select register. µ-Law mode is more commonly used in North America and Japan, and A-Law is primarily used in Europe and other countries ...
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... Value at Segment Endpoints Digital Code 8159 10000000b . . . 4319 4063 10001111b . . . 2143 2015 10011111b . . . 1055 991 10101111b . . . 511 479 10111111b . . . 239 223 11001111b . . . 103 95 11011111b . . . 35 31 11101111b . . . 3 1 11111110b 0 11111111b Preliminary Rev. 0.91 Si3220/Si3225 * Decode Level 8031 4191 2079 1023 495 231 ...
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... Si3220/Si3225 Table 39. A-Law Encode-Decode Characteristics Segment #intervals X interval size Number 128 Notes: 1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative values. 2. Digital code includes inversion of even numbered bits. Other available formats include inversion of odd bits, inversion of all bits bit inversion. See "PCM Companding" on page 70 for more details. ...
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... B1 and B2, one Monitor channel M GCI Data Receive used for initialization and setup of the device, and one Signaling and communicating status of the device and for initiating commands. Within the SC channel are six Command/ Preliminary Rev. 0.91 Si3220/Si3225 SDI SDO ...
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... Si3220/Si3225 Indicate (C/I) bits and two handshaking bits, MR and MX. The C/I bits indicate status and command communication, while the handshaking bits Monitor Receive (MR) and Monitor Transmit (MX), exchange data in the Monitor channel. Figure 55 illustrates the contents of a GCI highway frame. 16-Bit GCI Mode ...
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... This also maximizes communication speed. Because of the handshaking protocol required for successful communication, the data transfer rate using the Monitor channel is less than 8 kbps. 2nd Byte 3rd Byte ACK ACK 1st Byte 2nd Byte µ 125 s Preliminary Rev. 0.91 Si3220/Si3225 CH3 Unused ACK 3rd Byte 75 ...
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... Si3220/Si3225 The Idle state is achieved by the MX and MR bits being held inactive for two or more frames. When a transmission is initiated by a host device, an active state is seen on the downstream MX bit. This signals the Dual ProSLIC that a transmission has begun on the Monitor channel and it should begin accepting data from it. The ...
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... bit calcu lated and tran s m itted on d ata ups tream (D TX) line. MX received d ata dow n s trea lin e. LL: Las t look of m onitor b yte received line. ABT: Abort ind ication to in terna l s ource. Figure 58. Dual ProSLIC Monitor Receiver State Diagram Preliminary Rev. 0.91 Si3220/Si3225 Initial S tate bort ...
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... Si3220/Si3225 Idle RQT RQT RQT nth RQT Wait RQT bit received line. MX: MX bit calculated and expected line. MXR : MX bit s am pled line. C LS: C ollis ion w ithin the m onitor data byte line. R QT: R eques t for trans ion from internal s ource. ABT: Abort reques t/indication. ...
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M onitor Da ta Dow nstre a m $FF $FF $91 $91 $81 $81 $10 µ 125 s 1 Frame M X Dow nstre a m Bit M R Dow nstre a m Bit M onitor Da ta Upstre a ...
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M onitor Da ta Dow nstre a m $FF $FF $91 $91 $01 $01 $10 µ 125 s 1 Frame M X Dow nstre a m Bit M R Dow nstre a m Bit M onitor Da ta Upstre a ...
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... CMD[6:0] = 0000001: Read or Write from the Dual ProSLIC CMD[6:0] = 0000010-1111111: Reserved Register Address Byte The Register Address Byte has the following structure: MSB This byte contains the actual 8-bit address of the register to be read or written. Preliminary Rev. 0.91 Si3220/Si3225 MSB LSB ...
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... Si3220/Si3225 SC Channel The downstream and upstream SC channels are continuously carrying I/O information to and from the Dual ProSLIC during every frame. The upstream processor has immediate access to the receive (downstream) and transmit (upstream) data present on the Dual ProSLIC’s digital I/O port when used in GCI mode ...
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... SC channel byte to the OPEN state for two consecutive cycles and then resetting the downstream SC channel byte to the intended linefeed state for two consecutive Preliminary Rev. 0.91 Si3220/Si3225 thresholds and control the linefeed ...
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... Si3220/Si3225 cycles. If the Dual ProSLIC continues to automatically transition to the OPEN state, the power alarm threshold might be set incorrectly. If this problem persists after the power alarm settings are verified, a system fault is Table 45. Automatic Linefeed State Transitions Initiating Action Automatic Linefeed State Transition Loop closure detected On-hook active → ...
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... Using these measurement tools, a variety of other diagnostics functions can also be performed to meet the unique requirements of specific summarizes the ranges and capabilities of the signal generation and measurement tools. Preliminary Rev. 0.91 Si3220/Si3225 test signals, measures the line test and diagnostics signal generation and applications ...
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... Si3220/Si3225 Table 47. Summary of Signal Generation and Measurement Tools Function DC Current Generation DC Voltage Generation Audio Tone Generation Ringing Signal Generation 8-Bit DC/Low Frequency Monitor A/D Converter Programmable Timer AC Low Pass Filter 16-Bit Audio A/D Converter Transmit Path Notch Filter Transmit Path Bandpass Filter ...
Page 87
... The audio path offers a 2.5 V peak voltage measurement capability and a coarse attenuation stage for scenarios where the incoming signal amplitude must be attenuated by as much bring it into the allowable input range without clipping. Preliminary Rev. 0.91 Si3220/Si3225 DIAGPK DIAGDC DIAGAC = metallic (loop) voltage )/2 = longitudinal voltage 87 ...
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... Si3220/Si3225 ! Programmable timer. The Dual ProSLIC devices incorporate several digital oscillator circuits to program the on- and off-times of the ringing and pulse metering signals. The tone generation oscillator can be used to program a time period for averaging specific measured test parameters. ! Transmit audio path diagnostics filter. Transmit ...
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... Intermodulation distortion measurement (two- tone method). Measures the intermodulation distortion product in the presence of two tones. It can be implemented by programming the three IIR diagnostics filter stages to provide two notches at the two tone frequencies and a peak at the frequency of interest. Preliminary Rev. 0.91 Si3220/Si3225 89 ...
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... Any register not listed is reserved and must not be written. Default hex value is loaded to register following any RESET. Only registers ID, MSTREN, MSTRSTAT, and IRQ0 are valid while the PLL is not locked (MSTRSTAT[PLOCK]). 2. Reserved bit values are indeterminate. 3. Register address is in decimal. 4. Read only. 5. Protected bits. 6. Per channel bit(s). 7. Si3220 only. 90 Bit 7 Bit 6 Bit 5 Bit 4 Audio ATXMUTE Calibration CAL CALOFFR CALOFFT CALOFFRN ...
Page 91
... Any register not listed is reserved and must not be written. Default hex value is loaded to register following any RESET. Only registers ID, MSTREN, MSTRSTAT, and IRQ0 are valid while the PLL is not locked (MSTRSTAT[PLOCK]). 2. Reserved bit values are indeterminate. 3. Register address is in decimal. 4. Read only. 5. Protected bits. 6. Per channel bit(s). 7. Si3220 only. Bit 7 Bit 6 Bit 5 Bit 4 SPI PLLFLT FSFLT PCFLT 4 PLLFAULT FSFAULT PCFAULT ...
Page 92
... Any register not listed is reserved and must not be written. Default hex value is loaded to register following any RESET. Only registers ID, MSTREN, MSTRSTAT, and IRQ0 are valid while the PLL is not locked (MSTRSTAT[PLOCK]). 2. Reserved bit values are indeterminate. 3. Register address is in decimal. 4. Read only. 5. Protected bits. 6. Per channel bit(s). 7. Si3220 only. 92 Bit 7 Bit 6 Bit 5 Bit 4 PULSETI[7:0] Polarity Reversal RAM Access RAMADDR[7:0] RAMDAT[15:8] RAMDAT[7:0] Soft Reset ...
Page 93
... Any register not listed is reserved and must not be written. Default hex value is loaded to register following any RESET. Only registers ID, MSTREN, MSTRSTAT, and IRQ0 are valid while the PLL is not locked (MSTRSTAT[PLOCK]). 2. Reserved bit values are indeterminate. 3. Register address is in decimal. 4. Read only. 5. Protected bits. 6. Per channel bit(s). 7. Si3220 only. Bit 7 Bit 6 Bit 5 Bit 4 COEFFA1[7:0] COEFFA2[15:8] COEFFA2[7:0] COEFFB0[23:16] COEFFB0[15:8] COEFFB0[7:0] COEFFB1[23:16] COEFFB1[15:8] ...
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... For the Si3220, the RINGAMP RAM address location is used to store the amplitude of the internal ringing signal. For the Si3225, this address location stores the desired time relay between the last zero current crossing and the next opportunity to open the ringing relay. ...
Page 95
... For the Si3220, the RINGAMP RAM address location is used to store the amplitude of the internal ringing signal. For the Si3225, this address location stores the desired time relay between the last zero current crossing and the next opportunity to open the ringing relay. ...
Page 96
... For the Si3220, the RINGAMP RAM address location is used to store the amplitude of the internal ringing signal. For the Si3225, this address location stores the desired time relay between the last zero current crossing and the next opportunity to open the ringing relay. ...
Page 97
... For the Si3220, the RINGAMP RAM address location is used to store the amplitude of the internal ringing signal. For the Si3225, this address location stores the desired time relay between the last zero current crossing and the next opportunity to open the ringing relay. ...
Page 98
... For the Si3220, the RINGAMP RAM address location is used to store the amplitude of the internal ringing signal. For the Si3225, this address location stores the desired time relay between the last zero current crossing and the next opportunity to open the ringing relay. ...
Page 99
... For the Si3220, the RINGAMP RAM address location is used to store the amplitude of the internal ringing signal. For the Si3225, this address location stores the desired time relay between the last zero current crossing and the next opportunity to open the ringing relay. ...
Page 100
... For the Si3220, the RINGAMP RAM address location is used to store the amplitude of the internal ringing signal. For the Si3225, this address location stores the desired time relay between the last zero current crossing and the next opportunity to open the ringing relay. ...
Page 101
... Pin Descriptions: Si3220/ SVBATa 1 RPOa 2 RPIa 3 RNIa 4 RNOa 5 CAPPa 6 Si3220 CAPMa 7 QGND 8 64-Lead TQFP 9 IREF (epad) CAPMb 10 CAPPb 11 RNOb 12 13 RNIb RPIb 14 RPOb 15 SVBATb Pin Number(s) Symbol Si3220 Si3225 SVBATa, SVBATb 2,15 2,15 RPOa, RPOb RPIa, RPIb RNIa, RNIb RNOa, RNOb ...
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... Si3220/Si3225 Pin Number(s) Symbol Si3220 Si3225 9 9 IREF 17, 64 17, 64 STIPDCb, STIPDCa 18, 63 18, 63 STIPACb, STIPACa 19, 62 19, 62 SRINGACb, SRINGACa 20, 61 20, 61 SRINGDCb, SRINGDCa 21, 60 21, 60 ITIPNb, ITIPNa 22, 59 22, 59 IRINGNb, IRINGNa 23, 58 23, 58 ITIPPb, ITIPPa 24, 37, 24, 37, VDD2,VDD3, 42, 57 42, 57 ...
Page 103
... Serial port control data input. O Serial Data Daisy Chain. Enables multiple devices to use a single CS for serial port con- trol. Connect SDITHRU pin from master device to SDI pin of slave device. An internal pullup resistor holds this pin high during idle periods. Preliminary Rev. 0.91 Si3220/Si3225 103 ...
Page 104
... Si3220/Si3225 Pin Number(s) Symbol Si3220 Si3225 BLKRNG epad epad GND 104 Input/ Description Output I Chip Select. Active low. When inactive, SCLK and SDI are ignored and SDO is high impedance. When active, serial port is operational. I Ring Generator Sensing Input. Senses ring-trip condition when using centralized ring generator. ...
Page 105
... Main power supply for all internal circuitry. Connect supply. Decouple locally with a 0.1 µF/10 V capacitor. Battery Voltage Select. Connect to the BATSEL pin of the Si3220 or Si3225 through an external resistor to enable automatic battery switching. No connection is required when used with the Si3225 in a single battery system configuration. ...
Page 106
... Negative TIP Current Control. Connect to the ITIPN lead of the Si3220 or Si3225. Positive TIP Current Control. Connect to the ITIPP lead of the Si3220 or Si3225. Exposed Die Paddle Ground. For adequate thermal management, the exposed die paddle should be sol- dered to a PCB pad that is connected to low-impedance inner and/or back- side ground planes using multiple vias. See “ ...
Page 107
... Dual ProSLIC Selection Guide Part Description Number Si3200-KS Linefeed interface Si3200-BS Linefeed interface Si3220-KQ Dual ProSLIC Si3220-BQ Dual ProSLIC Si3225-KQ Dual ProSLIC Si3225-BQ Dual ProSLIC On-Chip External Pulse Metering Ringing Ringing Support " " " " " " Preliminary Rev. 0.91 ...
Page 108
... Si3220/Si3225 Package Outline: 64-Pin TQFP Figure 65 illustrates the package details for the Dual ProSLIC. Table 48 lists the values for the dimensions shown in the illustration See Detail A See Detail B Figure 65. 64-Pin Thin Quad Flat Package (TQFP) Table 48. 64-Pin Package Diagram Dimensions 108 ...
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... Min Max A 1.35 1.75 A1 .10 .25 A2 1.30 1.50 B .33 .51 C .19 .25 D 9.80 10.01 E 3.80 4.00 e 1.27 BSC H 5.80 6.20 h .25 .50 L .40 1.27 L1 1.07 BSC γ — 0.10 θ 0º 8º Preliminary Rev. 0.91 Si3220/Si3225 h 0.010 GAUGE PLANE C L1 See Detail F 109 ...
Page 110
... Si3220/Si3225 Document Change List Revision 0.9 to Revision 0.91 ! Table 8 on page 12 TIP/RING Pulldown Transistor Saturation Voltage " updated. TIP/RING Pullup Transistor Saturation Voltage updated. " Note added. " ! "Calculating Overhead Voltages" on page 27 Second paragraph updated. " ! "Internal Trapezoidal Ringing" on page 42 RINGAMP equation updated. ...
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... Notes: Preliminary Rev. 0.91 Si3220/Si3225 111 ...
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... Si3220/Si3225 Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...