DS2180A Maxim Integrated Products, DS2180A Datasheet
DS2180A
Specifications of DS2180A
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DS2180A Summary of contents
Page 1
... Receive error detection and counting for transmission performance monitoring 5V supply, low-power CMOS technology Surface-mount package available, designated DS2180AQ Industrial temperature range of - +85 C available, designated DS2180AN or DS2180AQN Compatible to DS2186 Transmit Line Interface, DS2187 Receive Line Interface, DS2188 Jitter Attenuator, DS2175 T1/CEPT Elastic Store, DS2290 T1 Isolation Stik, and ...
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... DESCRIPTION The DS2180A is a monolithic CMOS device designed to implement primary rate (1.544 MHz) T-carrier transmission systems. The 193S framing mode is intended to support existing Ft/Fs applications (12 frames/superframe). The 193E framing mode supports the extended superframe format (24 frames/superframe). Clear channel capability is provided by selection of appropriate zero suppression and signaling modes ...
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... SCLK, tri-stated during serial port write or when CS is high. Chip Select. Must be low to write or read the serial port registers. Serial Data Clock. Used to write or read the serial port registers. Serial Port Select. Tie select serial port. Tie mode DS2180A to select hardware SS ...
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... Receive Frame Error. High during F-Bit time when F or when FPS or CRC errors occur (193E). Low during resync. Receive Loss of Sync. Indicates sync status; high when internal resync is in progress, low otherwise DS2180A or F errors occur (193S ...
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... SERIAL PORT INTERFACE Pins 14 through 18 of the DS2180A serve as a microprocessor/microcontroller-compatible serial port. Sixteen onboard registers allow the user to update operational characteristics and monitor device status via host controller, minimizing hardware interfaces. Port read/write timing is unrelated to the system transmit and receive timing, allowing asynchronous reads and/or writes by the host ...
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... Burst Mode. If set (and ACB.1 through ACB.4=0) burst read or write is enabled. Reserved, must be 0 for proper operation. Reserved, must be 0 for proper operation. MSB of register address. LSB of register address. Read/Write Select write addressed register read addressed register ADD1 AD0 DS2180A (LSB ...
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... If CCR.1=0, no bit 7 stuffing occurs. (Note: This bit must be set to 0 when CCR.2=1) Loopback. When set, the device internally loops output transmit data into the incoming receive data buffers and TCLK is internally substituted for RCLK DS2180A (LSB) B8ZS B7 LPBK ...
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... B8ZS The DS2180A supports existing and emerging zero suppression formats. Selection of B8ZS coding maintains system 1’s density requirements without disturbing data integrity as required in emerging clear channel applications. B8ZS coding replaces eight consecutive outgoing 0's with a B8ZS code word. Any received B8ZS code word is replaced with all 0’s. B8ZS and bit 7 stuffing modes should not be enabled simultaneously ...
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... CH11 CH21 CH20 CH19 NAME AND DESCRIPTION Transmit Idle Registers. Each of these bit positions represents a DS0 channel in the outgoing frame. When set, the corresponding channel will output an idle code format determined by TCR. DS2180A (LSB) CH2 CH1 TIR1 CH10 CH9 TIR2 CH18 ...
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... TRANSMIT INSERTION HIERARCHY Figure DS2180A ...
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... TMO. 2. Channels in which robbed bit signaling is enabled will sample TABCD during the LSB bit time in frames indicated. 3. When external S-bit insertion is enabled, TLINK will be sampled during the F-bit time of even frames and inserted into the outgoing data stream DS2180A ...
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... If TMSYNC is tied low and TFSYNC is pulsed at frame boundaries, the transmitter will establish an arbitrary multiframe boundary as indicated by TMO. 2. Channels in which robbed bit signaling is enabled will sample TABCD during the LSB bit time in frames indicated. 3. TLINK is sampled during the F-bit time of odd frames and inserted into the outgoing data stream (FDL data DS2180A ...
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... TLINK timing shown is for 193E framing; in 193E framing, TLINK is sampled as indicated for insertion into F-bit position of odd frames. When S-bit insertion is enabled in 193S, TLINK is sampled during even frames TCR.5=1, TSER is sampled during the F-bit time of CRC frames for insertion into the outgoing data stream (193E framing only DS2180A ...
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... If set, no auto resync occurs. Resync. When toggled low to high, the transceiver will initiate resync immediately. The bit must be cleared, then set again for subsequent resyncs SYNCT SYNCE pattern, then search patterns in sync algorithm. S DS2180A (LSB) RESYNC ...
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... CH21 CH20 CH19 NAME AND DESCRIPTION Receive Mark Registers. Each of these bit positions represents a DS0 channel in the incoming T1 frame. When set, the corresponding channel will output codes determined by RCR.4 and RCR. DS2180A (LSB) CH2 CH1 RMR1 CH10 CH9 RMR2 CH18 CH17 ...
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... RECEIVE MULTIFRAME TIMING Figure 15 NOTES: 1. Signaling data is updated during signaling frames on channel boundaries. RABCD outputs the LSB of each channel word in non-signaling frames. 2. RLINK data (FDL-bit) is updated one bit time prior to odd frames and held for two frames DS2180A ...
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... RECEIVE MULTIFRAME BOUNDARY TIMING Figure 16 NOTES: 1. RLINK timing is shown for 193E; in 193S, RLINK is updated on even frame boundaries and is held across multiframe edges. 2. Total delay from RPOS and RNEG to RSER output is 13 RCLK periods DS2180A ...
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... Receive Loss of Sync. Set when resync is in process; if RCR.1=0, RLOS transitions high on an OOF event or carrier loss indicating auto resync DS2180A (LSB) B8ZSD RBL RLOS (193S) or FPS (193E) bit error ...
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... Frame Bit Error Mask Interrupt enabled Interrupt masked. B8ZS Detect Mask Interrupt enabled Interrupt masked. Receive Blue Alarm Mask Interrupt enabled Interrupt masked. Receive Loss of Sync Mask Interrupt enabled Interrupt masked. errors when RCR.3 errors only when RCR.3= DS2180A (LSB) B8ZSD RBL RLOS bits T ...
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... LSB of bipolar count. OOFD0 ESFD3 ESF ERROR COUNT NAME AND DESCRIPTION MSB of OOF event count. LSB of OOF event count. MSB of extended superframe error count. LSB of extended superframe error count DS2180A (LSB) BVD2 BVD1 BVD0 (LSB) ESFD2 ESFD1 ESFD0 and F errors when ...
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... RCL transitions high (during 32nd bit time) when 32 consecutive bits received are 0; RCL transitions low when the next 1 is received. and F patterns are tested. The FPS pattern is tested in 193E T S clears all registers and forces immediate receive resync when DS2180A returns RST must be held low on RST ...
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... RST input may be used to force immediate receiver RST NAME AND DESCRIPTION 3 193S – S-bit insertion 1 = external internal Framing Mode Select 193E 193S Transmit Yellow Alarm 1 = enabled disabled 1 Zero Suppression 1 = bit 7 stuffing 0 = transparent 1 B8ZS 1 = enabled disabled disables the serial port, clears DS2180A ...
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... T1 OVERVIEW Framing Standards The DS2180A is compatible with the existing Bell System D4 framing standard described in ATT PUB 43801 and the new extended superframe format (ESF) as described in ATT C.B. #142. In this document, D4 framing is referred to as 193S and ESF (also known as Fe) is referred to as 193E. Programmable features of the DS2180A allow support of other framing standards which are derivatives of 193E and 193S ...
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... BITS 1-8 C3 BITS 1-8 - BITS 1-8 - BITS 1-7 BIT 8 - BITS 1-8 C4 BITS 1-8 - BITS 1-8 - BITS 1-8 - BITS 1-8 C5 BITS 1-7 BIT 8 - BITS 1-8 - BITS 1-8 - BITS 1-8 C6 BITS 1-8 - BITS 1-8 - BITS 1-7 BIT DS2180A SIGNALING-BIT USE STATE STATE STATE ...
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... Bipolar violations occur in the fourth and seventh bit positions which are ignored by the DS2180A error monitoring logic when B8ZS is enabled. Any received B8ZS code word is replaced with all 0’s if B8ZS is enabled ...
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... In 193S framing, when RCR.3=1, the synchronizer will cross check the F help eliminate false framing candidates such as digital milliwatts. The F or FPS bits are in error. When RCR.1 is set, the automatic T . Note that using to initiate resync resets the receive output timing RST DS2180A pattern with the F pattern patterns are compared to the S ...
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... Average Reframe Time is defined here as the average time it takes from the start of sync (rising edge of RLOS) to the actual loading of the new alignment (on a multiframe edge) into the output receive timing. BACKPLANE INTERFACE USING DS2180A AND DS2176 Figure 22 patterns (101010...) without cross-coupling the F T ...
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... The circuit shown in Figure 23 “decouples” the processor timing from that of the DS2180A by use of a small FIFO memory. The processor writes to the FIFO (6 bytes are written: 3 for A data, 3 for B data) only when signaling updates are required. The system is interrupt-driven from the transmit multiframe sync input ...
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... SYMBOL MIN TYP 4.5 5.0 DD SYMBOL MIN TYP OUT ( SYMBOL MIN TYP MAX UNITS V +. +0 MAX UNITS 5.0V ± 10%) DD MAX UNITS µA 1 µ DS2180A NOTES =25 C) NOTES NOTES 1 ...
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... Shaded regions indicate “don’t care” states of input data. SYMBOL MIN CDH 250 CL t 250 CCH t 250 CWH t CDV t CDZ T 50 SCC =.8 V and 10 ns maximum rise and fall time 5.0V ± 10%) DD TYP MAX UNITS 500 200 DS2180A NOTES ...
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... NOTES: 1. Measured 2.0V Output load capacitance = 100 pF. 1 – TRANSMIT SYMBOL MIN t 250 125 WL STD t 50 HTD t -125 STS t PTS t PTCH t 100 TSP = .8V and 10 ns maximum rise and fall time 5.0V ± 10%) DD TYP MAX UNITS 648 ns 324 125 DS2180A NOTES ...
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... NOTES: 1. Measured 2.0V Output load capacitance = 100 pF. 1 – RECEIVE SYMBOL MIN t PRS t PRD t TTR t 250 125 WL SRD t 50 HRD t PRA t 1 RST = .8V and 10 ns maximum rise and fall times 5.0V ± 10%) DD TYP MAX UNITS 648 ns 324 µs DS2180A NOTES ...
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... TRANSMIT AC TIMING DIAGRAM RECEIVE AC TIMING DIAGRAM DS2180A ...
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... DS2180A SERIAL T1 TRANSCEIVER (600 MIL DIP) DIM INCHES MIN MAX 2.050 2.075 0.530 0.550 0.140 0.160 0.600 0.625 0.015 0.040 0.120 0.145 0.090 0.110 0.625 0.675 0.008 0.012 0.015 0.022 DS2180A ...
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... DS2180AQ SERIAL T1 TRANSCEIVER (PLCC) DIM CH1 INCHES MIN MAX 0.165 0.180 0.090 0.120 0.020 - 0.026 0.033 0.013 0.021 0.009 0.012 0.042 0.048 0.685 0.695 0.650 0.656 0.590 0.630 0.685 0.695 0.650 0.656 0.590 0.630 0.050 BSC DS2180A ...