DS21554L Maxim Integrated Products, DS21554L Datasheet - Page 80

• Manufacturer Part Number: DS21554L
• Description: IC TXRX E1 1-CHIP 5V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21554L

• Function: Single-Chip Transceiver
• Interface: E1, HDLC, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: Remote and AIS Alarm Detector / Generator
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -

15.
The line interface function in the DS21354/DS21554 contains three sections: (1) the receiver, which
handles clock and data recovery; (2) the transmitter, which waveshapes and drives the E1 line; and (3) the
jitter attenuator. Each of these three sections is controlled by The Line Interface Control Register (LICR)
contrlls each of these three sections.
LICR: LINE INTERFACE CONTROL REGISTER (Address = 18 Hex)
SYMBOL
(MSB)
JABDS
EGL
DJA
TPD
JAS
L2
L2
L1
L0
LINE INTERFACE FUNCTIONS
POSITION
LICR.7
LICR.6
LICR.5
LICR.4
LICR.3
LICR.2
LICR.1
LICR.0
L1
Line Build-Out Select Bit 2. Sets the transmitter build out (see
and
Line Build-Out Select Bit 1. Sets the transmitter build out (see
and
Line Build-Out Select Bit 0. Sets the transmitter build out (see
and
Receive Equalizer Gain Limit.
0 = -12dB
1 = -43dB
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
Jitter Attenuator Buffer Depth Select.
0 = 128 bits
1 = 32 bits (use for delay sensitive applications)
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
Transmit Power Down.
0 = normal transmitter operation
1 = powers down the transmitter and tri-states the TTIP and TRING pins
L0
Table
Table
Table
15-2).
15-2).
15-2).
EGL
80 of 124
NAME AND DESCRIPTION
JAS
JABDS
DJA
Table 15-1
Table 15-1
Table 15-1
(LSB)
TPD