DS3172+ Maxim Integrated Products, DS3172+ Datasheet - Page 5

• Manufacturer Part Number: DS3172+
• Description: IC TXRX DS3/E3 DUAL 400-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3172+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 2
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 328mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

10.3 R
10.4 G
10.5 P
10.6 DS3/E3 F
10.7 HDLC O
10.8 T
10.9 FEAC C
10.10 L
10.2.2 Sources of Clock Output Pin Signals ................................................................................................... 54
10.2.3 Line IO Pin Timing Source Selection ................................................................................................... 57
10.2.4 Clock Structures On Signal IO Pins ..................................................................................................... 59
10.2.5 Gapped Clocks..................................................................................................................................... 60
10.4.1 Clock Rate Adapter (CLAD)................................................................................................................. 63
10.4.2 8 kHz Reference Generation ............................................................................................................... 64
10.4.3 One Second Reference Generation..................................................................................................... 66
10.4.4 General-Purpose IO Pins ..................................................................................................................... 66
10.4.5 Performance Monitor Counter Update Details ..................................................................................... 67
10.4.6 Transmit Manual Error Insertion .......................................................................................................... 68
10.5.1 Loopbacks............................................................................................................................................ 69
10.5.2 Loss Of Signal Propagation ................................................................................................................. 71
10.5.3 AIS Logic.............................................................................................................................................. 71
10.5.4 Loop Timing Mode ............................................................................................................................... 74
10.5.5 HDLC Overhead Controller .................................................................................................................. 74
10.5.6 Trail Trace ............................................................................................................................................ 74
10.5.7 BERT.................................................................................................................................................... 74
10.5.8 SCT port pins ....................................................................................................................................... 74
10.5.9 Framing Modes .................................................................................................................................... 76
10.5.10 Line Interface Modes............................................................................................................................ 76
10.6.1 General Description ............................................................................................................................. 78
10.6.2 Features ............................................................................................................................................... 78
10.6.3 Transmit Formatter............................................................................................................................... 79
10.6.4 Receive Framer.................................................................................................................................... 79
10.6.5 C-Bit DS3 Framer/Formatter ................................................................................................................ 83
10.6.6 M23 DS3 Framer/Formatter ................................................................................................................. 86
10.6.7 G.751 E3 Framer/Formatter................................................................................................................. 88
10.6.8 G.832 E3 Framer/Formatter................................................................................................................. 90
10.7.1 General Description ............................................................................................................................. 96
10.7.2 Features ............................................................................................................................................... 96
10.7.3 Transmit FIFO ...................................................................................................................................... 97
10.7.4 Transmit HDLC Overhead Processor .................................................................................................. 97
10.7.5 Receive HDLC Overhead Processor ................................................................................................... 98
10.7.6 Receive FIFO ....................................................................................................................................... 98
10.8.1 General Description ............................................................................................................................. 99
10.8.2 Features ............................................................................................................................................... 99
10.8.3 Functional Description........................................................................................................................ 100
10.8.4 Transmit Data Storage ....................................................................................................................... 100
10.8.5 Transmit Trace ID Processor ............................................................................................................. 100
10.8.6 Transmit Trail Trace Processing ........................................................................................................ 100
10.8.7 Receive Trace ID Processor .............................................................................................................. 100
10.8.8 Receive Trail Trace Processing ......................................................................................................... 101
10.8.9 Receive Data Storage ........................................................................................................................ 101
10.9.1 General Description ........................................................................................................................... 102
10.9.2 Features ............................................................................................................................................. 102
10.9.3 Functional Description........................................................................................................................ 102
10.10.1 General Description ........................................................................................................................... 104
10.10.2 Features ............................................................................................................................................. 104
10.10.3 B3ZS/HDB3 Encoder ......................................................................................................................... 104
INE
RAIL
ER
ESET AND
LOBAL
P
E
T
ORT
NCODER
RACE
R
ONTROLLER
VERHEAD
ESOURCES
RAMER
R
P
ESOURCES
OWER
C
/D
ONTROLLER
ECODER
/ F
C
-D
ONTROLLER
ORMATTER
..................................................................................................................................... 63
................................................................................................................................... 102
OWN
................................................................................................................................. 69
............................................................................................................................ 104
............................................................................................................................ 60
............................................................................................................................ 99
..................................................................................................................... 78
.................................................................................................................... 96
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