DS3174 Maxim Integrated Products, DS3174 Datasheet - Page 182
DS3174
Manufacturer Part Number
DS3174
Description
IC QUAD DS3/E3 TXRX 400-PBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3171N.pdf
(234 pages)
Specifications of DS3174
Function
Single-Chip Transceiver
Interface
DS3, E3
Number Of Circuits
4
Voltage - Supply
3.135 V ~ 3.465 V
Current - Supply
725mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
400-BGA
Includes
DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
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Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 11: C-bit Parity Error Latched (CPEL) – This bit is set when a C-bit parity error is detected. This bit is set to
zero in M23 DS3 mode.
Bit 10: Remote Error Indication Latched (FBEL) – This bit is set when a far-end block error is detected. This bit
is set to zero in M23 DS3 mode.
Bit 9: P-bit Parity Error Latched (PEL) – This bit is set when a P-bit parity error is detected.
Bit 8: Framing Error Latched (FEL) – This bit is set when a framing error is detected. The type of framing error
event that causes this bit to be set is determined by T3.RCR.FECC[1:0]
Bit 3: C-bit Parity Error Count Latched (CPECL) – This bit is set when the CPEC bit transitions from zero to one.
This bit is set to zero in M23 DS3 mode.
Bit 2: Remote Error Indication Count Latched (FBECL) – This bit is set when the FBEC bit transitions from zero
to one. This bit is set to zero in M23 DS3 mode.
Bit 1: P-bit Parity Error Count Latched (PECL) – This bit is set when the PEC bit transitions from zero to one.
Bit 0: Framing Error Count Latched (FECL) – This bit is set when the FEC bit transitions from zero to one.
15
--
--
7
14
--
--
6
T3.RSRL2
T3 Receive Status Register Latched #2
(1,3,5,7)2Ah
13
--
--
5
12
--
--
4
182
CPECL
CPEL
11
3
FBECL
FBEL
10
2
PECL
PEL
9
1
FECL
FEL
8
0
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