PEB20320H-V34RF Infineon Technologies, PEB20320H-V34RF Datasheet - Page 15
PEB20320H-V34RF
Manufacturer Part Number
PEB20320H-V34RF
Description
IC CONTROLR 32-CH HDLC 160-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB20320H-V34.pdf
(252 pages)
Specifications of PEB20320H-V34RF
Function
Multichannel Network Interface Controller (MUNICH)
Interface
HDLC, ISDN, V.110, X.30
Voltage - Supply
5V
Current - Supply
100mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
160-BSQFP
Includes
Automatic Flag Detection, CRC Generation and Checking, Error Detection, Interframe-Time-Fill Change Detection
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Power (watts)
-
Number Of Circuits
-
Other names
PEB20320H-V34RF
PEB20320H-V34RFIN
PEB20320H-V34RFIN
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Pin Definitions and Functions (cont’d)
Pin No.
P-MQFP-160-1
90
75
User’s Manual
Symbol
W/R
R/W
READY
DSACK
Output (O)
Input (I)
O
O
I
I
15
Function
Write/Read (Intel bus mode)
This signal distinguishes write from read
operations.
Read/Write (Motorola bus mode)
This signal distinguishes between read
and write operations.
In both cases this signal is tristate when
unused.
Ready (Intel bus mode)
This signal indicates that the current bus
cycle is complete. When READY is
asserted during a read cycle the
MUNICH32 latches the input data and
terminates the cycle. When READY is
asserted during a write cycle the
MUNICH32 terminates the cycle.
Data Transfer Acknowledge (Motorola
bus mode)
This active low input indicates that a data
transfer may be performed. During a read
cycle data becomes valid at the falling
edge of DSACK. The data is latched
internally and the bus cycle is terminated.
During a write cycle the falling edge of
DSACK marks the latching of data and the
bus cycle is terminated.
Introduction
PEB 20320
01.2000
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